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PCM5102APWR

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by Ray

Texas Instruments ADCs/DACs - Special Purpose, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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PCM5102APWR

Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-20

PCM5102APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPVDD power_in Charge pump power supply, 3.3 V nominal (3.1 V-3.46 V). Powers the internal DirectPath charge pump that generates the negative rail for ground-centered outputs. Referenced to CPGND.
2 CAPP passive Charge pump flying capacitor terminal for the positive rail. Connect the flying capacitor between CAPP and CAPM.
3 CPGND power_in Charge pump ground return. Must be tied to system ground (within 0.2 V of other grounds).
4 CAPM passive Charge pump flying capacitor terminal for the negative rail. Connect the flying capacitor between CAPP and CAPM.
5 VNEG power_out Negative charge-pump rail output, nominally −3.3 V. Requires a decoupling capacitor to CPGND; do not load externally.
6 OUTL output Analog line-level output from the DAC left channel. 2.1 VRMS full-scale, ground-centered (no DC blocking cap required). Load 1 kΩ min, 10 kΩ typ.
7 OUTR output Analog line-level output from the DAC right channel. 2.1 VRMS full-scale, ground-centered (no DC blocking cap required). Load 1 kΩ min, 10 kΩ typ.
8 AVDD power_in Analog power supply, 3.3 V nominal (3.0-3.46 V in VCOM mode). Referenced to AGND.
9 AGND power_in Analog ground. Tie to system ground; all grounds must be within 0.2 V of each other.
10 DEMP input De-emphasis control for 44.1 kHz sampling rate. Low = de-emphasis off, High = de-emphasis on. Failsafe LVCMOS Schmitt-trigger input.
11 FLT input Digital filter select. Low = normal latency (20 tS), High = low latency (3.5 tS). Failsafe LVCMOS Schmitt-trigger input.
12 SCK input System (master) clock input, up to 50 MHz. Failsafe LVCMOS Schmitt-trigger input. Tie low to use the internal PLL-generated clock referenced to BCK.
13 BCK input Audio serial-port bit clock input (I²S BCK). Failsafe LVCMOS Schmitt-trigger input.
14 DIN input Audio serial-port data input (I²S / Left-justified PCM). Failsafe LVCMOS Schmitt-trigger input; accepts 16-, 24-, or 32-bit data.
15 LRCK input Audio serial-port word (frame) clock input (L/R clock). Failsafe LVCMOS Schmitt-trigger input.
16 FMT input Audio data format select. Low = I²S, High = Left-justified. Failsafe LVCMOS Schmitt-trigger input.
17 XSMT input Soft mute control (active low). Low = soft mute, High = soft un-mute. Failsafe LVCMOS Schmitt-trigger input; used to gate the analog mute for pop-free start/stop.
18 LDOO power_out Internal LDO output for logic supply rail - used for decoupling when running the internal 1.8 V regulator, or connect an external 1.8 V supply here when bypassing the LDO.
19 DGND power_in Digital ground. Tie to system ground; all grounds must be within 0.2 V of each other.
20 DVDD power_in Digital power supply, 1.8 V (1.65-1.95 V) or 3.3 V (3.1-3.46 V) referenced to DGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • PCM5102APWR

CAD (KiCad official)

  • Symbol: PCM5102APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 a522083606b8e994, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF