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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

L99DZ100GPTR

STMicroelectronics · Power Management - Specialized · LQFP-64(10x10)

L99DZ100GPTR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	WU	input	Wake-up input for static or cyclic monitoring of external contacts, rated for DC wake-up voltage of -0.3 to +28 V (load dump 40 V).
2	CP2M	passive	Charge pump pin for capacitor 2, negative side.
3	CP2P	passive	Charge pump pin for capacitor 2, positive side.
4	CP	power_out	Charge pump output.
5	CP1P	passive	Charge pump pin for capacitor 1, positive side.
6	CP1M	passive	Charge pump pin for capacitor 1, negative side.
7	GHheater	output	Gate driver for an external power N-channel MOSFET in high-side configuration to control the heater.
8	SHheater	passive	Source of the high-side MOSFET used to control the heater.
9	OUT14	output	High-side driver output to drive LEDs.
10	OUT13	output	High-side driver output to drive LEDs.
11	OUT12	output	High-side driver output to drive LEDs.
12	OUT9	output	High-side driver output to drive LEDs.
13	OUT10	output	High-side driver output; besides the OUT10_x bits in CR5, this output can be switched on by the ECON bit for electro-chrome control mode, which has higher priority.
14	OUT11	output	High-side driver output to drive LEDs.
15	LS1_FSO	output	Fail-safe low-side switch (active low); output voltage range -0.3 to 35 V.
16	LS2_FSO	output	Fail-safe low-side switch (active low); output voltage range -0.3 to 35 V.
17	VS	power_in	Power supply for the power stage outputs; external reverse battery protection is required, a ceramic capacitor close to GND is recommended, and all VS pins must be connected externally for full output current capability.
18	VS	power_in	Second VS pin for power stage supply current capability; must be connected externally together with all other VS pins.
19	OUT7	output	High-side driver output to drive LEDs or a 10 W bulb (programmable Rdson).
20	OUT6	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
21	OUT1	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
22	OUT2	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
23	OUT5	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
24	OUT5	output	Second OUT5 pin providing additional current capability for the same half-bridge output.
25	VSREG	power_in	Power supply for the internal voltage regulators, OUT15 and OUT_HS; external reverse battery protection (diode) is required and an electrolytic back-up capacitor is recommended.
26	OUT_HS	output	High-side driver output to drive LEDs or to supply contacts (buffered supply).
27	OUT4	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
28	OUT4	output	Second OUT4 pin providing additional current capability for the same half-bridge output.
29	OUT3	output	Half-bridge output built from an internally connected high-side and low-side power DMOS switch, each with an internal parasitic reverse diode.
30	VS	power_in	Third VS pin for power stage supply current capability; must be connected externally together with all other VS pins.
31	OUT15	output	High-side driver output to drive LEDs.
32	PGND	power_in	Power ground.
33	OUT8	output	High-side driver output to drive LEDs or a 5 W bulb (programmable Rdson).
34	ECDR	output	In EC control mode, this pin drives the gate of an external N-channel MOSFET; absolute maximum output voltage -0.3 to VS+0.3 V.
35	SGND	power_in	Signal ground.
36	CM	output	Current monitor output that sources an image of the instantaneous current through the high-side driver selected by CM_SEL_x (CR7) at a fixed ratio.
37	ECV	input	Voltage monitor input for electro-chrome control mode; an additional low-side switch is implemented for fast discharge.
38	CLK	input	SPI serial clock input, up to 4 MHz.
39	DO	output	SPI serial data output (push-pull output stage); high impedance when CSN is high.
40	DI	input	SPI serial data input, sampled on the rising edge of CLK.
41	CSN	input	SPI chip select (not) input; a low level starts a communication frame.
42	TxD_L	input	LIN transmit data input.
43	RxD_L/NINT	output	RxDL: LIN receive data output; NINT: indicates local/remote wake-up events (push-pull output stage).
44	TxD_C	input	CAN transmit data input.
45	RxD_C/NINT	output	CAN receive data output; NINT indicates local/remote wake-up events (push-pull output stage).
46	DIR1	input	Direct drive input 1.
47	PWMH	input	PWMH input used to control the H-bridge gate drivers.
48	DIRH	input	Direction input controlling the H-bridge drivers for the external MOSFETs.
49	DIR2	input	Direct drive input 2.
50	NRESET	output	Reset output to the microcontroller (reset state LOW); low-side switch with internal pull-up to 5V_1.
51	5V_1	power_out	Voltage regulator 1 output providing 5 V supply, e.g. for the microcontroller and CAN transceiver.
52	CAN	power_in	CAN supply input allowing an external CAN supply from the V1 or V2 regulator; CAN supply absolute maximum -0.3 to +5.25 V.
53	NINT	output	Interrupt output (active low, push-pull) indicating VSREG early warning in active mode and wake-up events from V1_standby mode.
54	CAN_L	bidirectional	CAN low-level bus voltage I/O; bus voltage range -27 to +40 V.
55	CAN_H	bidirectional	CAN high-level bus voltage I/O; bus voltage range -27 to +40 V.
56	Debug	input	Debug input to deactivate the window watchdog (active high); debug input voltage range -0.3 to 40 V.
57	LIN	bidirectional	LIN bus line; LIN bus I/O voltage range -20 to +40 V.
58	5V_2	power_out	Voltage regulator 2 output providing a 5 V supply for external loads (potentiometer, sensors) or the CAN transceiver; protected against reverse supply.
59	GL1	output	Gate driver for the PowerMOS low-side switch in half-bridge 1.
60	SH1	passive	Source of the high-side switch in half-bridge 1.
61	GH1	output	Gate driver for the PowerMOS high-side switch in half-bridge 1.
62	GH2	output	Gate driver for the PowerMOS high-side switch in half-bridge 2.
63	SH2	passive	Source of the high-side switch in half-bridge 2.
64	GL2	output	Gate driver for the PowerMOS low-side switch in half-bridge 2.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Power Management (PMIC)
Pins	64

CAD (KiCad official)

Symbol: L99DZ100GPTR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: l99dz100gptr-etched.step / l99dz100gptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l99dz100gptr.step / l99dz100gptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (197 pp, sha256 d078940241be0c50, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF