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Contents

README

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TLV5631IPW

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-20

TLV5631IPW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Digital ground reference for the serial interface and digital logic.
2 DIN input Digital serial data input; the 16-bit word (4 control and 12 data bits) is shifted in MSB first on the falling edges of SCLK.
3 SCLK input Serial clock input, with a maximum serial clock frequency of 30 MHz.
4 FS input Frame sync input; a falling edge starts the write cycle, and in µC mode FS must be held low until all 16 data bits are transferred.
5 PRE input Preset input, asynchronous to the clock; driving it low while LDAC is asserted sets the DAC outputs to the value in the preset register.
6 OUTE output DAC output E, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
7 OUTF output DAC output F, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
8 OUTG output DAC output G, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
9 OUTH output DAC output H, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
10 AGND power_in Analog ground reference for the DAC resistor strings and output amplifiers.
11 AVDD power_in Analog power supply: 4.5 V to 5.5 V for 5 V operation or 2.7 V to 3.3 V for 3 V operation; AVDD must come up before DVDD for correct power-on reset.
12 OUTA output DAC output A, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
13 OUTB output DAC output B, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
14 OUTC output DAC output C, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
15 OUTD output DAC output D, a rail-to-rail buffered output (gain of two) that reliably drives a 2 kΩ load with 100 pF load capacitance.
16 REF bidirectional Voltage reference input/output: accepts an external reference up to AVDD, or outputs the internal 1.024 V or 2.048 V reference (up to 1 mA), which needs a 1 µF to 10 µF capacitor in parallel with 100 pF.
17 MODE input DSP/µC mode select: High = µC mode, not connected = DSP mode.
18 LDAC input Load DAC input; the DAC outputs are updated only while this asynchronous input is low.
19 DOUT output Digital serial data output that repeats the DIN data with a 16-clock-cycle delay for daisy-chaining when enabled through the CTRL0 DO bit.
20 DVDD power_in Digital power supply: 4.5 V to 5.5 V for 5 V operation or 2.7 V to 3.3 V for 3 V operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: TLV5631IPW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tlv5631ipw-etched.step / tlv5631ipw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv5631ipw.step / tlv5631ipw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 fca921911e680eae, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF