Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN65MLVD047PW

Texas Instruments · LVDS ICs · TSSOP-16

SN65MLVD047PW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Driver enable input (active high, per the function table with EN̅); LVTTL input with VIH of 2 V to VCC and VIL of 0 to 0.8 V.
2	1A	input	Channel 1 LVTTL driver data input, VIH 2 V to VCC and VIL 0 to 0.8 V, with a built-in 360-kΩ pull-down.
3	2A	input	Channel 2 LVTTL driver data input, VIH 2 V to VCC and VIL 0 to 0.8 V, with a built-in 360-kΩ pull-down.
4	VCC	power_in	Supply voltage input, 3 V to 3.6 V (3.3 V nominal); absolute maximum -0.5 V to 4 V.
5	GND	power_in	Circuit ground, the reference for all voltage values except differential bus voltages.
6	3A	input	Channel 3 LVTTL driver data input, VIH 2 V to VCC and VIL 0 to 0.8 V, with a built-in 360-kΩ pull-down.
7	4A	input	Channel 4 LVTTL driver data input, VIH 2 V to VCC and VIL 0 to 0.8 V, with a built-in 360-kΩ pull-down.
8	EN̅	input	Driver enable input (active low, per the function table with EN); drivers are high-impedance when EN is high or open.
9	4Z	tri_state	Channel 4 M-LVDS inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
10	4Y	tri_state	Channel 4 M-LVDS non-inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
11	3Y	tri_state	Channel 3 M-LVDS non-inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
12	3Z	tri_state	Channel 3 M-LVDS inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
13	2Z	tri_state	Channel 2 M-LVDS inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
14	2Y	tri_state	Channel 2 M-LVDS non-inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
15	1Y	tri_state	Channel 1 M-LVDS non-inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.
16	1Z	tri_state	Channel 1 M-LVDS inverting bus output, high-impedance when disabled, rated for 9-kV HBM ESD and bus range -1.4 V to 3.8 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Interface
Pins	16

CAD (KiCad official)

Symbol: SN65MLVD047PW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: sn65mlvd047pw-etched.step / sn65mlvd047pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd047pw.step / sn65mlvd047pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (23 pp, sha256 0e7e8558fd435b2d, retrieved 2026-10-07, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF