component
STM32F100C4T6B
Public Unreviewedby Ray
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
README
markdownSTM32F100C4T6B
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32F100C4T6B from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery supply for RTC and backup registers when VDD is off. Typical 1.8-3.6 V. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 (default) with optional TAMPER-RTC alternate function. Supplied by the power switch on the backup domain and limited to 3 mA sink current at ≤2 MHz. |
| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14 (default) or LSE 32.768 kHz oscillator input (OSC32_IN). Backup-domain pin with restricted drive. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15 (default) or LSE 32.768 kHz oscillator output (OSC32_OUT). Backup-domain pin with restricted drive. |
| 5 | PD0-OSC_IN | input | HSE crystal oscillator input (OSC_IN, 4-24 MHz) after reset; can be remapped to GPIO PD0 by software. |
| 6 | PD1-OSC_OUT | output | HSE crystal oscillator output (OSC_OUT) after reset; can be remapped to GPIO PD1 by software. |
| 7 | NRST | bidirectional | Bidirectional device reset input / open-drain output, active low. Internal weak pull-up to VDD. |
| 8 | VSSA | power_in | Analog ground reference for ADC, DAC and VREF circuits. Tie to system ground. |
| 9 | VDDA | power_in | Analog supply for ADC, DAC, reset block, PLL and VREF. 2.0-3.6 V, must be tied at or above VDD. |
| 10 | PA0-WKUP | bidirectional | GPIO PA0 / Standby wake-up input (WKUP). Alternate: USART2_CTS, ADC1_IN0, TIM2_CH1_ETR. |
| 11 | PA1 | bidirectional | GPIO PA1. Alternate: USART2_RTS, ADC1_IN1, TIM2_CH2. |
| 12 | PA2 | bidirectional | GPIO PA2. Alternate: USART2_TX, ADC1_IN2, TIM2_CH3, TIM15_CH1. |
| 13 | PA3 | bidirectional | GPIO PA3. Alternate: USART2_RX, ADC1_IN3, TIM2_CH4, TIM15_CH2. |
| 14 | PA4 | bidirectional | GPIO PA4. Alternate: SPI1_NSS, USART2_CK, ADC1_IN4, DAC1_OUT. |
| 15 | PA5 | bidirectional | GPIO PA5. Alternate: SPI1_SCK, ADC1_IN5, DAC2_OUT. |
| 16 | PA6 | bidirectional | GPIO PA6. Default alt: SPI1_MISO, ADC1_IN6, TIM3_CH1. Remap: TIM1_BKIN, TIM16_CH1. |
| 17 | PA7 | bidirectional | GPIO PA7. Default alt: SPI1_MOSI, ADC1_IN7, TIM3_CH2. Remap: TIM1_CH1N, TIM17_CH1. |
| 18 | PB0 | bidirectional | GPIO PB0. Default alt: ADC1_IN8, TIM3_CH3. Remap: TIM1_CH2N. |
| 19 | PB1 | bidirectional | GPIO PB1. Default alt: ADC1_IN9, TIM3_CH4. Remap: TIM1_CH3N. |
| 20 | PB2/BOOT1 | bidirectional | GPIO PB2. Also read as BOOT1 during reset to select boot mode together with BOOT0. |
| 21 | PB10 | bidirectional | GPIO PB10. Default alt: I2C2_SCL, USART3_TX. Remap: TIM2_CH3, HDMI_CEC. |
| 22 | PB11 | bidirectional | GPIO PB11. Default alt: I2C2_SDA, USART3_RX. Remap: TIM2_CH4. |
| 23 | VSS_1 | power_in | Digital ground. |
| 24 | VDD_1 | power_in | Digital supply, 2.0-3.6 V. Decouple with 100 nF close to the pin. |
| 25 | PB12 | bidirectional | GPIO PB12. Default alt: SPI2_NSS, I2C2_SMBA, TIM1_BKIN, USART3_CK. (SPI2/I2C2 not present on low-density value line.) |
| 26 | PB13 | bidirectional | GPIO PB13. Default alt: SPI2_SCK, TIM1_CH1N, USART3_CTS. |
| 27 | PB14 | bidirectional | GPIO PB14. Default alt: SPI2_MISO, TIM1_CH2N, USART3_RTS. Remap: TIM15_CH1. |
| 28 | PB15 | bidirectional | GPIO PB15. Default alt: SPI2_MOSI, TIM1_CH3N, TIM15_CH1N. Remap: TIM15_CH2. |
| 29 | PA8 | bidirectional | GPIO PA8. Alt: USART1_CK, MCO (master clock output), TIM1_CH1. |
| 30 | PA9 | bidirectional | GPIO PA9. Alt: USART1_TX, TIM1_CH2, TIM15_BKIN. |
| 31 | PA10 | bidirectional | GPIO PA10. Alt: USART1_RX, TIM1_CH3, TIM17_BKIN. |
| 32 | PA11 | bidirectional | GPIO PA11. Alt: USART1_CTS, TIM1_CH4. |
| 33 | PA12 | bidirectional | GPIO PA12. Alt: USART1_RTS, TIM1_ETR. |
| 34 | PA13 | bidirectional | JTMS-SWDIO debug pin after reset (JTAG mode select / Serial Wire data). Can be remapped to GPIO PA13. |
| 35 | VSS_2 | power_in | Digital ground. |
| 36 | VDD_2 | power_in | Digital supply, 2.0-3.6 V. Decouple with 100 nF close to the pin. |
| 37 | PA14 | bidirectional | JTCK-SWCLK debug pin after reset (JTAG clock / Serial Wire clock). Can be remapped to GPIO PA14. |
| 38 | PA15 | bidirectional | JTDI debug pin after reset. Alt as PA15/SPI1_NSS/TIM2_CH1_ETR when JTAG is disabled. |
| 39 | PB3 | bidirectional | JTDO/TRACESWO debug pin after reset. Alt: PB3/TIM2_CH2/SPI1_SCK when JTAG is disabled. |
| 40 | PB4 | bidirectional | NJTRST debug pin (active-low JTAG reset) after reset. Alt: PB4/TIM3_CH1/SPI1_MISO when NJTRST is released. |
| 41 | PB5 | bidirectional | GPIO PB5 (non-FT, standard I/O only). Default alt: I2C1_SMBA, TIM16_BKIN. Remap: TIM3_CH2, SPI1_MOSI. |
| 42 | PB6 | bidirectional | GPIO PB6. Default alt: I2C1_SCL, TIM4_CH1, TIM16_CH1N. Remap: USART1_TX. |
| 43 | PB7 | bidirectional | GPIO PB7. Default alt: I2C1_SDA, TIM17_CH1N, TIM4_CH2. Remap: USART1_RX. |
| 44 | BOOT0 | input | Boot mode selection input, sampled at reset with BOOT1 to choose main flash / system memory / SRAM boot. |
| 45 | PB8 | bidirectional | GPIO PB8. Default alt: TIM4_CH3, TIM16_CH1, CEC. Remap: I2C1_SCL. |
| 46 | PB9 | bidirectional | GPIO PB9. Default alt: TIM4_CH4, TIM17_CH1. Remap: I2C1_SDA. |
| 47 | VSS_3 | power_in | Digital ground. |
| 48 | VDD_3 | power_in | Digital supply, 2.0-3.6 V. Decouple with 100 nF close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | MCU |
| Pins | 48 |
Ordering variants
Same part, different packaging or reel option.
STM32F100C4T6BSTM32F100C4T6BT7STM32F100C4T6BT7BSTM32F100C4T6BRSTM32F100C4T6BVSTM32F100C4T6BH
CAD (KiCad official)
- Symbol:
STM32F100C4T6B - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (88 pp, sha256
c810aafb848820fa, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).