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ESP32-D0WDQ6

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Espressif Systems RF Transceiver ICs, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ESP32-D0WDQ6

Espressif Systems · RF Transceiver ICs · QFN-48-EP(6x6)

ESP32-D0WDQ6 from Espressif Systems, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Analog supply pin, 2.3 V to 3.6 V.
2 LNA_IN bidirectional RF input to the low-noise amplifier and RF output from the power amplifier.
3 VDD3P3 power_in Analog supply pin, 2.3 V to 3.6 V.
4 VDD3P3 power_in Analog supply pin, 2.3 V to 3.6 V.
5 SENSOR_VP input Input-only pin (GPIO36, ADC1_CH0, RTC_GPIO0) with no output driver and no internal pull-up or pull-down.
6 SENSOR_CAPP input Input-only pin (GPIO37, ADC1_CH1, RTC_GPIO1) with no output driver and no internal pull-up or pull-down.
7 SENSOR_CAPN input Input-only pin (GPIO38, ADC1_CH2, RTC_GPIO2) with no output driver and no internal pull-up or pull-down.
8 SENSOR_VN input Input-only pin (GPIO39, ADC1_CH3, RTC_GPIO3) with no output driver and no internal pull-up or pull-down.
9 CHIP_PU input Chip enable: high enables the chip and low shuts it down (VIL_nRST max 0.6 V); the pin must not be left floating.
10 VDET_1 input Input-only pin (GPIO34, ADC1_CH6, RTC_GPIO4) with no output driver and no internal pull-up or pull-down.
11 VDET_2 input Input-only pin (GPIO35, ADC1_CH7, RTC_GPIO5) with no output driver and no internal pull-up or pull-down.
12 32K_XP bidirectional GPIO32 / ADC1_CH4 / RTC_GPIO9 / TOUCH9, also the 32.768 kHz crystal input for RTC.
13 32K_XN bidirectional GPIO33 / ADC1_CH5 / RTC_GPIO8 / TOUCH8, also the 32.768 kHz crystal output for RTC.
14 GPIO25 bidirectional General-purpose I/O (also ADC2_CH8, RTC_GPIO6, DAC_1, EMAC_RXD0).
15 GPIO26 bidirectional General-purpose I/O (also ADC2_CH9, RTC_GPIO7, DAC_2, EMAC_RXD1).
16 GPIO27 bidirectional General-purpose I/O (also ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV).
17 MTMS bidirectional GPIO14 general-purpose I/O, also JTAG MTMS, ADC2_CH6, TOUCH6, HSPICLK and SD_CLK (SDIO host 2).
18 MTDI bidirectional GPIO12 general-purpose I/O, also JTAG MTDI and strapping pin that selects VDD_SDIO voltage at reset (0 = VDD3P3_RTC, 1 = 1.8 V LDO).
19 VDD3P3_RTC power_in RTC IO and CPU supply input, 2.3 V to 3.6 V.
20 MTCK bidirectional GPIO13 general-purpose I/O, also JTAG MTCK, ADC2_CH4 and TOUCH4.
21 MTDO bidirectional GPIO15 general-purpose I/O, also JTAG MTDO and strapping pin that controls U0TXD printing at boot.
22 GPIO2 bidirectional General-purpose I/O and strapping pin that selects boot mode together with GPIO0 (default pull-down, 0).
23 GPIO0 bidirectional General-purpose I/O and strapping pin that selects boot mode together with GPIO2 (default pull-up, 1).
24 GPIO4 bidirectional General-purpose I/O (also ADC2_CH0, TOUCH0, HSPIHD, HS2_DATA1, SD_DATA1).
25 GPIO16 bidirectional General-purpose I/O (also HS1_DATA4, U2RXD, EMAC_CLK_OUT); a pull-up is required if used for PSRAM CE#.
26 VDD_SDIO power_out Output of the internal LDO (1.8 V, max 40 mA, 1.65 V to 2.0 V) or VDD3P3_RTC, powering flash/PSRAM and IO; can also be supplied externally.
27 GPIO17 bidirectional General-purpose I/O (also HS1_DATA5, U2TXD, EMAC_CLK_OUT_180).
28 SD_DATA_2 bidirectional SDIO slave data line 2 (GPIO9, SPIHD); used for in-package flash/PSRAM and not recommended for other use.
29 SD_DATA_3 bidirectional SDIO slave data line 3 (GPIO10, SPIWP); used for in-package flash/PSRAM and not recommended for other use.
30 SD_CMD bidirectional SDIO slave command line (GPIO11, SPICS0); used for in-package flash/PSRAM and not recommended for other use.
31 SD_CLK bidirectional SDIO slave clock (GPIO6, SPICLK); used for in-package flash/PSRAM and not recommended for other use.
32 SD_DATA_0 bidirectional SDIO slave data line 0 (GPIO7, SPIQ); used for in-package flash/PSRAM and not recommended for other use.
33 SD_DATA_1 bidirectional SDIO slave data line 1 (GPIO8, SPID); used for in-package flash/PSRAM and not recommended for other use.
34 GPIO5 bidirectional General-purpose I/O and strapping pin for SDIO slave timing (also HS1_DATA6, VSPICS0, EMAC_RX_CLK).
35 GPIO18 bidirectional General-purpose I/O (also HS1_DATA7 and VSPICLK).
36 GPIO23 bidirectional General-purpose I/O (also HS1_STROBE and VSPID).
37 VDD3P3_CPU power_in CPU IO supply input, 1.8 V to 3.6 V.
38 GPIO19 bidirectional General-purpose I/O (also U0CTS, VSPIQ, EMAC_TXD0).
39 GPIO22 bidirectional General-purpose I/O (also U0RTS, VSPIWP, EMAC_TXD1).
40 U0RXD bidirectional UART0 receive signal, also GPIO3 and CLK_OUT2.
41 U0TXD bidirectional UART0 transmit signal, also GPIO1, CLK_OUT3 and EMAC_RXD2.
42 GPIO21 bidirectional General-purpose I/O (also VSPIHD and EMAC_TX_EN).
43 VDDA power_in Analog supply pin, 2.3 V to 3.6 V.
44 XTAL_N output External main crystal oscillator output; with Wi-Fi/BT only a 40 MHz crystal is supported.
45 XTAL_P input External main crystal oscillator input; with Wi-Fi/BT only a 40 MHz crystal is supported.
46 VDDA power_in Analog supply pin, 2.3 V to 3.6 V.
47 CAP2 passive Connects a 3.3 nF (10%) capacitor in parallel with a 20 kΩ resistor to CAP1.
48 CAP1 passive Connects a 10 nF capacitor in series to ground.
49 GND power_in Ground (exposed thermal pad on the QFN-48 6x6 package).

Key specifications

Parameter Value
Manufacturer Espressif Systems
Package QFN-48-EP(6x6)
Category RF And Wireless
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Recommended input voltage, VDD3P3_CPU VDD3P3_CPU 1.8 3.3 3.6 V 50
Total input current IV DD 0.5 A 50
Operating temperature T -40 125 °C note 3: chips without embedded flash/PSRAM 50
Allowable input voltage (VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU, VDD_SDIO) -0.3 3.6 V 50
IO total output current Ioutput 1200 mA note 1: 25 °C, 24 h, all IO pins held high and grounded 50
Storage temperature TSTORE -40 150 °C 50
Low-level input voltage VIL -0.3 V (3.3 V, 25 °C) 51
High-level input current IIH 50 nA (3.3 V, 25 °C) 51
Low-level input current IIL 50 nA (3.3 V, 25 °C) 51
Low-level input voltage that shuts down the chip (CHIP_PU) VIL_nRST 0.6 V 51
Pin capacitance CIN 2 pF (3.3 V, 25 °C) 51
High-level source current, VDD3P3_CPU power domain IOH 40 mA VDD1 = 3.3 V, VOH >= 2.64 V, pin output strength set to max; note 2 51
High-level source current, VDD3P3_RTC power domain IOH 40 mA VDD1 = 3.3 V, VOH >= 2.64 V, pin output strength set to max; note 2 51
High-level source current, VDD_SDIO power domain IOH 20 mA VDD1 = 3.3 V, VOH >= 2.64 V, pin output strength set to max; note 3 51
Low-level sink current IOL 28 mA VDD1 = 3.3 V, VOL = 0.495 V, pin output strength set to max 51
Pull-up resistor RPU 45 kΩ 51
Pull-down resistor RPD 45 kΩ 51
ESD sensitivity, HBM (human body model) -2000 2000 V JS-001 52
ESD sensitivity, CDM (charged device model) -500 500 V JS-002 52
Latch-up overcurrent -200 200 mA JESD78, overcurrent 52
Operating channel center frequency range 2412 2484 MHz note 1: per national/regional regulations 52
Output power, 11b mode 18.5 19.5 20.5 dBm 11b mode 52
Output power, 11n MCS7 12 13 14 dBm 11n, MCS7 52
RF transmit power control range (BR) -12 9 dBm 53
Δf1avg (BR) Δf1avg 155 kHz 53
Out-of-band blocking, 30 MHz to 2000 MHz -10 dBm 30 MHz ~ 2000 MHz 55
Out-of-band blocking, 2000 MHz to 2400 MHz -27 dBm 2000 MHz ~ 2400 MHz 55
Out-of-band blocking, 2500 MHz to 3000 MHz -27 dBm 2500 MHz ~ 3000 MHz 55
Out-of-band blocking, 3000 MHz to 12.5 GHz -10 dBm 3000 MHz ~ 12.5 GHz 55
Δf1avg (BLE) Δf1avg 265 kHz 56

CAD (KiCad official)

  • Symbol: ESP32-D0WDQ6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm
  • 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: esp32-d0wdq6-etched.step / esp32-d0wdq6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-d0wdq6.step / esp32-d0wdq6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Espressif Systems datasheet (74 pp, sha256 bac015371d876744, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF