BQ40Z80RSMT from Texas Instruments, in a VQFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VC5	input	Cell-voltage sense input for the fifth cell from the bottom that supplies balancing current for that cell and returns balancing current for the sixth cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the fifth cell's positive terminal and to VC4 (tie to VC4 if unused), with a VC5-VC4 input range of -0.2 V to 5 V.
2	VC4	input	Cell-voltage sense input for the fourth cell from the bottom that supplies balancing current for that cell and returns balancing current for the fifth cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the fourth cell's positive terminal and to VC3 (tie to VC3 if unused), with a VC4-VC3 input range of -0.2 V to 5 V.
3	VC3	input	Cell-voltage sense input for the third cell from the bottom that supplies balancing current for that cell and returns balancing current for the fourth cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the third cell's positive terminal and to VC2 (tie to VC2 if unused), with a VC3-VC2 input range of -0.2 V to 5 V.
4	VC2	input	Cell-voltage sense input for the second cell from the bottom that supplies balancing current for that cell and returns balancing current for the third cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the second cell's positive terminal and to VC1 (tie to VC1 if unused), with a VC2-VC1 input range of -0.2 V to 5 V.
5	VC1	input	Cell-voltage sense input for the bottom cell that supplies balancing current for that cell and returns balancing current for the second cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the bottom cell's positive terminal and to VSS, with a VC1-VSS input range of -0.2 V to 5 V.
6	SRN	input	Analog input to the internal coulomb counter that senses the small voltage between SRP and SRN, with charge current flowing from SRP to SRN; connect through an RC filter to the sense-resistor terminal tied to PACK- (not CELL-), with an SRP/SRN input range of -0.2 V to 0.2 V.
7	NC	unconnected	No internal connection.
8	SRP	input	Analog input to the internal coulomb counter that senses the small voltage between SRP and SRN, where SRP is the top of the sense resistor; connect through an RC filter to the sense-resistor terminal tied to the minimum positive cell negative terminal, with an SRP/SRN input range of -0.2 V to 0.2 V.
9	VSS	power_in	Device ground.
10	TS1	input	Temperature sensor 1 thermistor input connected to thermistor-1; if unused, connect directly to VSS and configure the data flash accordingly.
11	TS2	input	Temperature sensor 2 thermistor input connected to thermistor-2; if unused, connect directly to VSS and configure the data flash accordingly.
12	TS3/ADCIN1/GPIO	bidirectional	Multifunction pin configurable through control registers as TS3 thermistor-3 input, ADCIN1 general-purpose ADC input for a properly scaled signal, or customizable GPIO; if unused, connect directly to VSS and configure the data flash accordingly.
13	DISP/TS4/ADCIN2/GPIO	bidirectional	Multifunction pin configurable through control registers as display button or LED connection (DISP), TS4 thermistor-4 input, ADCIN2 general-purpose ADC input for a properly scaled signal, or customizable GPIO; if unused, connect directly to VSS and configure the data flash accordingly.
14	NC	unconnected	No internal connection.
15	DISP/GPIO	bidirectional	Open-drain multifunction pin for a display button or LED connection (DISP) or customizable GPIO, configurable through control registers; if unused, connect directly to VSS and configure the data flash accordingly.
16	PDSG/GPIO	bidirectional	Open-drain multifunction pin that drives an N-channel FET to control PRE-DISCHARGE mode (PDSG) or serves as customizable GPIO, configurable through control registers; if unused, connect directly to VSS and configure the data flash accordingly.
17	PRES/SHUTDN/DISP/PDSG/GPIO	bidirectional	Open-drain multifunction pin serving as system-present input (PRES, connected to the host to detect a removable pack; do not pull up), embedded-pack emergency shutdown input (SHUTDN), display button or LED control (DISP), pre-discharge control (PDSG), or GPIO; if unused, connect directly to VSS and configure the data flash accordingly.
18	SMBD	bidirectional	Open-drain SMBus data pin with a recommended input voltage range up to 32 V.
19	SMBC	bidirectional	Open-drain SMBus clock pin with a recommended input voltage range up to 32 V.
20	LEDCNTLA/PDSG/GPIO	output	Multifunction pin for LED display segment LEDCNTLA (drives external LEDs per firmware configuration), pre-discharge PDSG control, or customizable GPIO, with a constant-current sink of 22.5 mA typical (15.75 mA to 29.25 mA); if unused, connect VSS through a 20 kΩ resistor.
21	LEDCNTLB/GPIO	output	Multifunction pin for LED display segment LEDCNTLB (drives external LEDs per firmware configuration) or customizable GPIO, with a constant-current sink of 22.5 mA typical (15.75 mA to 29.25 mA); if unused, connect VSS through a 20 kΩ resistor.
22	LEDCNTLC/GPIO	output	Multifunction pin for LED display segment LEDCNTLC (drives external LEDs per firmware configuration) or customizable GPIO, with a constant-current sink of 22.5 mA typical (15.75 mA to 29.25 mA); if unused, connect VSS through a 20 kΩ resistor.
23	FUSE	output	Fuse-driver output that can be ORed with a secondary protector in the fuse N-channel FET gate driver and releases a typical 8 V output when the device commands the chemical fuse to ignite; if unused, connect directly to VSS.
24	VCC	power_in	Auxiliary power input connected through a series resistor to the midpoint of the protection FETs, with an operating supply range of 2.2 V to 32 V.
25	PACK	input	Battery-pack detection analog input connected to PACK+ through a series resistor, with a PACK-VSS input range of -0.2 V to 32 V.
26	DSG	output	NMOS discharge FET drive output connected to the gate of the DSG FET.
27	NC	unconnected	No internal connection.
28	PCHG	output	PMOS precharge FET drive output connected to the PCHG FET gate when precharge is used; leave floating if unused.
29	CHG	output	NMOS charge FET drive output connected to the gate of the CHG FET.
30	BAT	power_in	Main power input connected through a diode and series resistor to the top of the battery pack, with an operating input range of 2.2 V to 32 V.
31	PBI	power_in	Power-backup input that supplies power during brief transient power interruptions; connect a 2.2 µF capacitor from PBI to VSS, with an operating range of 2.2 V to 32 V.
32	VC6	input	Cell-voltage sense input for the sixth cell from the bottom that supplies balancing current for that cell; connect through a 100 Ω series resistor and 0.1 µF capacitor to the sixth cell's positive terminal and to VC5 (tie to VC5 if unused), with a VC6-VSS input range of -0.2 V to 30 V.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32(4x4)
Category	Power Management
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VCC (BAT, VCC, PBI, PACK pins)	VCC	2.2		32	V	BAT, VCC, PBI, PACK pins; min/max over TA = -40 to 85 °C	9
Shutdown voltage (falling)	VSHUTDOWN-	1.8	2	2.2	V	VPACK < VSHUTDOWN-	9
Shutdown start voltage (rising)	VSHUTDOWN+	2.05	2.25	2.45	V	VPACK > VSHUTDOWN- + VHYS	9
Analog input voltage range SRP, SRN	VIN	-0.2		0.2	V	SRP, SRN pins	9
Operating temperature	TOPR	-40		85	°C		9
BAT to VCC switchover voltage (falling)	VSWITCHOVER-	1.95	2.1	2.2	V	VBAT < VSWITCHOVER-	10
VCC to BAT switchover voltage (rising)	VSWITCHOVER+	2.9	3.1	3.25	V	VBAT > VSWITCHOVER- + VHYS	10
Internal pull-down resistance PACK	RPD	30	40	50	kΩ	PACK	10
AFE power-on reset time	tRST	200	300	400	µs		10
Internal 1.8 V LDO regulator voltage	VREG	1.6	1.8	2	V		10
Regulator output voltage variation over temperature	ΔVO(TEMP)	-0.25		0.25	%	ΔVREG / ΔTA, IREG = 10mA	10
Regulator line regulation	ΔVO(LINE)	-0.6		0.5	%	ΔVREG / ΔVBAT, IBAT = 10mA	10
Regulator load regulation	ΔVO(LOAD)	-1.5		1.5	%	ΔVREG / ΔIREG, IREG = 0 mA to 10 mA	11
Regulator short-circuit current limit	ISC	25	40	55	mA	VREG = 0 × VREG(NOM)	11
Internal voltage reference 1	VREF1	1.215	1.22	1.225	V	TA = 25°C, trimmed	11
VREF1 drift	VREF1(DRIFT)	-50		50	PPM/°C	TA = 0°C to 60°C, trimmed	11
VREF1 drift	VREF1(DRIFT)	-80		80	PPM/°C	TA = -40°C to 85°C, trimmed	11
Internal voltage reference 2	VREF2	1.22	1.225	1.23	V	TA = 25°C, trimmed	11
VREF2 drift	VREF2(DRIFT)	-50		50	PPM/°C	TA = 0°C to 60°C, trimmed	11
VREF2 drift	VREF2(DRIFT)	-80		80	PPM/°C	TA = -40°C to 85°C, trimmed	11
Scale factor K, VC1-VSS through VC5-VC4	K	0.198	0.2	0.202	-	VC1-VSS, VC2-VC1, VC3-VC2, VC4-VC3, VC5-VC4, VC6-VC5	11
Scale factor K, VC6-VSS	K	0.032	0.0333	0.034	-	VC6-VSS	11
Scale factor K, BAT and PACK	K	0.0275	0.0286	0.0295	-	BAT-VSS, PACK-VSS	11
Scale factor K, VREF2	K	0.49	0.5	0.51	-	VREF2	11
ADC input voltage range (cell and VC inputs)	VIN	-0.2		5	V	VC1-VSS, VC2-VC1, VC3-VC2, VC4-VC3, VC5-VC4, VC6-VC5	11
ADC input voltage range VC6-VSS	VIN	-0.2		30	V	VC6-VSS	11
ADC input voltage range PACK-VSS	VIN	-0.2		32	V	PACK-VSS	11
ADC integral nonlinearity (16-bit, best fit)	INL	-8.5		8.5	LSB	16-bit, best fit, -0.1 V to 0.8 × VREF1	11
ADC integral nonlinearity (16-bit, best fit)	INL	-13.1		13.1	LSB	16-bit, best fit, -0.2 V to -0.1 V	11
Current wake threshold	VWAKE	0.3	0.625	0.9	mV	VWAKE = VSRP, VSRN = ±0.625 mV; magnitude as printed	12
Current wake threshold	VWAKE	2.4	5	7.2	mV	VWAKE = VSRP, VSRN = ±5 mV; magnitude as printed	12
Coulomb counter input voltage range	VINPUT	-0.1		0.1	V		12
Thermistor pull-up resistor TS1	RNTC(PU)	14.4	18	21.6	kΩ	TS1	14
Thermistor pull-up resistor TS2	RNTC(PU)	14.4	18	21.6	kΩ	TS2	14
Thermistor pull-up resistor TS3	RNTC(PU)	14.4	18	21.6	kΩ	TS3	14
Thermistor pull-up resistor TS4	RNTC(PU)	14.4	18	21.6	kΩ	TS4	14
Thermistor pull-up resistance drift	RNTC(DRIFT)	-360	-280	-200	PPM/°C		14
LEDCNTLx high-side output current protection	ISC	-30	-45	-60	mA	LEDCNTLx	14
LEDCNTLx low-side output current	IOL	15.75	22.5	29.25	mA	LEDCNTLx, VBAT > 3.0V, VOL > 0.4V	14
Thermal shutdown	tSHUTDOWN	120	135	150	°C	LEDCNTLx, by design	14
GPIO high-side output current protection	ISC	-30	-45	-60	mA	GPIO (pins 20, 21, 22), PDSG on pin 20	15
GPIO low-side output current	IOL	15.75	22.5	29.25	mA	VBAT > 3.0V, VOL > 0.4V	15
SMBus operating frequency (slave)	fSMB	10		100	kHz	SLAVE mode, SMBC 50% duty cycle	15
SMBus error signal detect time	tTIMEOUT	25		35	ms		15
FUSE driver output voltage high	VOH	6	7	8.65	V	VBAT ≥ 8V, CL = 1nF, IAFEFUSE = 0µA	16
FUSE driver input voltage high	VIH	1.5	2	2.5	V		16
FUSE driver output impedance	RAFEFUSE	2	2.6	3.2	kΩ		16
CHG/DSG N-channel gate voltage ratio DSG	RatioDSG	2.133	2.333	2.45	-	RatioDSG = (VDSG, VBAT) / VBAT, 2.2V < VBAT < 4.92V, 10MΩ between PACK and DSG	16
CHG/DSG N-channel gate voltage ratio CHG	RatioCHG	2.133	2.333	2.433	-	RatioCHG = (VCHG, VBAT) / VBAT, 2.2V < VBAT < 4.92V, 10MΩ between BAT and CHG	16
DSG output voltage, FET on	VDSG(ON)	10.5	11.5	12.5	V	VBAT ≥ 4.92V (up to 32V), 10MΩ between PACK and DSG	16
CHG output voltage, FET on	VCHG(ON)	10.5	11.5	12.5	V	VBAT ≥ 4.92V (up to 32V), 10MΩ between BAT and CHG	16
DSG output voltage, FET off	VDSG(OFF)	-0.4		0.4	V	VDSG(OFF) = (VDSG, VPACK), 10MΩ between PACK and DSG	16
CHG output voltage, FET off	VCHG(OFF)	-0.4		0.4	V	VCHG(OFF) = (VCHG, VBAT), 10MΩ between BAT and CHG	16
Power-channel PCHG gate voltage, FET on	VFETON	6	7	8	V	VPCHG(ON) = VCC, VPCHG, VBAT ≥ 8V, 10MΩ between VCC and CHG	16
Thermal resistance, junction to ambient, high-K	RθJA		47.4		°C/W		9
Thermal resistance, junction to case (top)	RθJC(top)		40.3		°C/W		9
Thermal resistance, junction to board	RθJB		14.7		°C/W		9
Thermal characterization, junction to board	ψJB		14.4		°C/W		9
Thermal resistance, junction to case (bottom)	RθJC(bottom)		3.8		°C/W		9

CAD (KiCad official)

Symbol: BQ40Z80RSMT
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32(4x4) (KiCad packages3D, STEP)
3D model files: bq40z80rsmt-etched.step / bq40z80rsmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq40z80rsmt.step / bq40z80rsmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (49 pp, sha256 91afbd94ad765fcf, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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BQ40Z80RSMT

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