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CY22392FXIT

Public Made by Adom

by adom

Infineon Cypress Semicon Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CY22392FXIT

Infineon Cypress Semicon · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16

CY22392FXIT from Infineon Cypress Semicon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKC output Configurable clock output C; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance.
2 VDD power_in Power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and all VDD pins must reach the specified voltage with monotonic ramps.
3 AGND power_in Analog ground; all grounds must be connected to the same ground plane.
4 XTALIN input Reference crystal input or external reference clock input; crystal range is 8 MHz to 30 MHz, and an external reference clock is 1 MHz to 166 MHz (commercial) or 1 MHz to 150 MHz (industrial) with a 40% to 60% duty cycle.
5 XTALOUT output Reference crystal feedback; for a driven clock input, XTALOUT must be left floating.
6 XBUF output Buffered reference clock output, which is simply the buffered reference.
7 CLKD output Configurable clock output D; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance.
8 CLKE output Configurable clock output E; it is sourced from PLL1 through a post divider programmable to /2, /3, or /4, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance.
9 CLKB output Configurable clock output B; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance.
10 CLKA output Configurable clock output A; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance.
11 GND power_in Ground; all grounds must be connected to the same ground plane.
12 S0 input General Purpose Input for frequency control, bit 0, used with S1 and S2 to select among eight programmed frequency settings.
13 S1 input General Purpose Input for frequency control, bit 1, used with S0 and S2 to select among eight programmed frequency settings.
14 AVDD power_in Analog power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and the maximum DC input voltage is limited to AVDD + 0.5 V.
15 S2/SUSPEND input General Purpose Input for frequency control, bit 2; optionally a suspend mode control input that shuts off a configured set of outputs and/or PLLs when LOW.
16 SHUTDOWN/OE input Places outputs in three-state and shuts down the chip when Low; optionally, it only tristates the outputs without shutting down the chip, and the three-state timing is 300 ns maximum.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package TSSOP-16
Category Clock/Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD/AVDD) VDD/AVDD 3.135 3.3 3.465 V 5
Industrial Operating Temperature, Ambient TA -40 85 C Industrial operating temperature, ambient 5
Maximum Load Capacitance CLOAD_OUT 15 pF 5
External Reference Crystal Frequency fREF 8 30 MHz External reference crystal 5
External Reference Clock Frequency, Industrial fREF 1 150 MHz External reference clock, Industrial 5
Power up time for all VDD's tPU 0.05 500 ms Time for all VDD's to reach minimum specified voltage; power ramps must be monotonic 5
Output High Current IOH 12 24 mA VOH = VDD, 0.5 V, VDD = 3.3 V 6
Output Low Current IOL 12 24 mA VOL = 0.5 V, VDD = 3.3 V 6
High Level Input Voltage VIH 70 % CMOS levels, % of AVDD 6
Low Level Input Voltage VIL 30 % CMOS levels, % of AVDD 6
Input High Current IIH 10 µA VIN = AVDD, 0.3 V 6
Input Low Current IIL 10 µA VIN = +0.3 V 6
Output Leakage Current IOZ 10 µA Three-state outputs 6
Total Power Supply Current in Shutdown Mode IDDS 5 20 µA Shutdown active 6
Output Frequency (Industrial clock output limit) 1/t1 166 MHz Clock output limit, Industrial 6
Output Duty Cycle t2 45 50 55 % Fout < 100 MHz, divider > 2, measured at VDD/2 6
Output Duty Cycle t2 40 50 60 % Fout > 100 MHz or divider = 1, measured at VDD/2 6
Rising Edge Slew Rate t3 0.75 1.4 V/ns Output clock rise time, 20% to 80% of VDD 6
Falling Edge Slew Rate t4 0.75 1.4 V/ns Output clock fall time, 80% to 20% of VDD 6
Output three-state Timing t5 150 300 ns Time for output to enter or leave three-state mode after SHUTDOWN/OE switches 6
Lock Time t7 1 3 ms PLL lock time from power up 6
Supply Voltage (absolute maximum) -0.5 7 V 5
DC Input Voltage -0.5 V Upper limit is AVDD + 0.5 V 5
Storage Temperature -65 125 C 5
Junction Temperature 125 C 5
Data Retention 10 years Tj = 125 C 5
Maximum Programming Cycles 100 cycles 5
Package Power Dissipation 350 mW 5
Static Discharge Voltage 2000 V Per MIL-STD-883, Method 3015 5
Latch up -200 200 mA According to JEDEC 17; printed as > ±200 mA 5
Package thermal resistance (junction to ambient) JA 115 C/W Package JA, per Junction Temperature Limitations section 5

CAD (KiCad official)

  • Symbol: CY22392FXIT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cy22392fxit-etched.step / cy22392fxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy22392fxit.step / cy22392fxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (14 pp, sha256 0cac945e21946252, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF