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PIC24FJ32GA002T-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), SSOP-28-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

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PIC24FJ32GA002T-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil

PIC24FJ32GA002T-I from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLR input Master Clear (device Reset) input, active-low. Drive low to force a device Reset. Typically pulled to VDD through a 10 kΩ resistor with an optional ICSP programming cable connection.
2 AN0/VREF+/CN2/RA0 bidirectional PORTA digital I/O RA0. Multiplexed with A/D analog input AN0, positive A/D and comparator reference VREF+, and Interrupt-on-Change input CN2. Schmitt-trigger digital input; analog level input/output when analog function selected.
3 AN1/VREF-/CN3/RA1 bidirectional PORTA digital I/O RA1. Multiplexed with A/D analog input AN1, negative A/D and comparator reference VREF-, and Interrupt-on-Change input CN3.
4 PGED1/AN2/C2IN-/RP0/CN4/RB0 bidirectional PORTB digital I/O RB0. Multiplexed with ICSP/ICD Programming Data channel 1 (PGED1), A/D input AN2, comparator 2 negative input C2IN-, Remappable Peripheral RP0, and Interrupt-on-Change CN4.
5 PGEC1/AN3/C2IN+/RP1/CN5/RB1 bidirectional PORTB digital I/O RB1. Multiplexed with ICSP/ICD Programming Clock channel 1 (PGEC1), A/D input AN3, comparator 2 positive input C2IN+, Remappable Peripheral RP1, and Interrupt-on-Change CN5.
6 AN4/C1IN-/SDA2/RP2/CN6/RB2 bidirectional PORTB digital I/O RB2. Multiplexed with A/D input AN4, comparator 1 negative input C1IN-, alternate I2C2 data SDA2, Remappable Peripheral RP2, and Interrupt-on-Change CN6.
7 AN5/C1IN+/SCL2/RP3/CN7/RB3 bidirectional PORTB digital I/O RB3. Multiplexed with A/D input AN5, comparator 1 positive input C1IN+, alternate I2C2 clock SCL2, Remappable Peripheral RP3, and Interrupt-on-Change CN7.
8 VSS power_in Ground reference for logic and I/O pins. Connect to system ground with low-inductance decoupling.
9 OSCI/CLKI/CN30/RA2 bidirectional PORTA digital I/O RA2. Alternate function: primary oscillator crystal input OSCI or external clock input CLKI; also Interrupt-on-Change CN30. Analog buffer when clock function is selected.
10 OSCO/CLKO/PMA0/CN29/RA3 bidirectional PORTA digital I/O RA3. Alternate function: primary oscillator output OSCO or divided system clock output CLKO; also Parallel Master Port address bit 0 (PMA0) and Interrupt-on-Change CN29.
11 SOSCI/RP4/PMBE/CN1/RB4 bidirectional PORTB digital I/O RB4. Multiplexed with Secondary Oscillator/Timer1 input SOSCI, Remappable Peripheral RP4, PMP byte enable strobe PMBE, and Interrupt-on-Change CN1.
12 SOSCO/T1CK/CN0/PMA1/RA4 bidirectional PORTA digital I/O RA4. Multiplexed with Secondary Oscillator/Timer1 output SOSCO, Timer1 external clock input T1CK, PMP address bit 1 (PMA1), and Interrupt-on-Change CN0.
13 VDD power_in Positive supply for peripheral digital logic and I/O pins. Operating range 2.0V to 3.6V. Decouple with 0.1 µF ceramic per VDD pin.
14 PGED3/ASDA1/RP5/CN27/PMD7/RB5 bidirectional PORTB digital I/O RB5. Multiplexed with ICSP Programming Data channel 3 (PGED3), alternate I2C1 data ASDA1, Remappable Peripheral RP5, PMP data bit 7 (PMD7), and Interrupt-on-Change CN27.
15 PGEC3/ASCL1/RP6/CN24/PMD6/RB6 bidirectional PORTB digital I/O RB6. Multiplexed with ICSP Programming Clock channel 3 (PGEC3), alternate I2C1 clock ASCL1, Remappable Peripheral RP6, PMP data bit 6 (PMD6), and Interrupt-on-Change CN24.
16 INT0/RP7/CN23/PMD5/RB7 bidirectional PORTB digital I/O RB7. Multiplexed with external interrupt INT0, Remappable Peripheral RP7, PMP data bit 5 (PMD5), and Interrupt-on-Change CN23.
17 TCK/SCL1/RP8/CN22/PMD4/RB8 bidirectional PORTB digital I/O RB8. Multiplexed with JTAG Test Clock (TCK), primary I2C1 clock SCL1, Remappable Peripheral RP8, PMP data bit 4 (PMD4), and Interrupt-on-Change CN22.
18 TDO/SDA1/RP9/CN21/PMD3/RB9 bidirectional PORTB digital I/O RB9. Multiplexed with JTAG Test Data Output (TDO), primary I2C1 data SDA1, Remappable Peripheral RP9, PMP data bit 3 (PMD3), and Interrupt-on-Change CN21.
19 DISVREG input Voltage Regulator Disable input. Tie to VSS to enable the on-chip 2.5V core regulator (VDD 2.5V-3.6V); tie to VDD to disable the regulator when VDD is at core voltage (2.0V-2.75V, apply VDDCORE externally to pin 20).
20 VCAP/VDDCORE power_in Core logic supply. With on-chip regulator enabled (DISVREG=0): connect a 10 µF low-ESR filter capacitor to VSS. With regulator disabled (DISVREG=1): apply external core supply (typically 2.5V) to this pin.
21 PGED2/TDI/RP10/CN16/PMD2/RB10 bidirectional PORTB digital I/O RB10. Multiplexed with ICSP Programming Data channel 2 (PGED2), JTAG Test Data Input (TDI), Remappable Peripheral RP10, PMP data bit 2 (PMD2), and Interrupt-on-Change CN16.
22 PGEC2/TMS/RP11/CN15/PMD1/RB11 bidirectional PORTB digital I/O RB11. Multiplexed with ICSP Programming Clock channel 2 (PGEC2), JTAG Test Mode Select (TMS), Remappable Peripheral RP11, PMP data bit 1 (PMD1), and Interrupt-on-Change CN15.
23 AN12/RP12/CN14/PMD0/RB12 bidirectional PORTB digital I/O RB12. Multiplexed with A/D input AN12, Remappable Peripheral RP12, PMP data bit 0 (PMD0), and Interrupt-on-Change CN14.
24 AN11/RP13/CN13/PMRD/RB13 bidirectional PORTB digital I/O RB13. Multiplexed with A/D input AN11, Remappable Peripheral RP13, PMP Read Strobe (PMRD), and Interrupt-on-Change CN13.
25 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14 bidirectional PORTB digital I/O RB14. Multiplexed with A/D input AN10, Comparator Voltage Reference output CVREF, Real-Time Clock/Calendar alarm output RTCC, Remappable Peripheral RP14, PMP Write Strobe (PMWR), and Interrupt-on-Change CN12.
26 AN9/RP15/CN11/PMCS1/RB15 bidirectional PORTB digital I/O RB15. Multiplexed with A/D input AN9, Remappable Peripheral RP15, PMP Chip Select 1 / Address bit 14 (PMCS1), and Interrupt-on-Change CN11.
27 VSS power_in Ground reference for logic and I/O pins. Second VSS pin on the 28-pin package; tie to the same ground plane as pin 8.
28 VDD power_in Positive supply for peripheral digital logic and I/O pins. Second VDD pin on the 28-pin package; decouple with 0.1 µF ceramic close to the pin.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SSOP-28-208mil
Category Embedded Processors & Controllers
Pins 28

Ordering variants

Same part, different packaging or reel option.

  • PIC24FJ32GA002T-II/SP
  • PIC24FJ32GA002T-I/SS
  • PIC24FJ32GA002T-II/SS
  • PIC24FJ32GA002T-I/SO
  • PIC24FJ32GA002T-II/SO
  • PIC24FJ32GA002T-I/ML
  • PIC24FJ32GA002T-II/ML

CAD (KiCad official)

  • Symbol: PIC24FJ32GA002T-I
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (278 pp, sha256 67fd2ef41e1a2d3f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF