Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74ALS00ADBR

Texas Instruments · Logic Gates · SSOP-14-208mil

SN74ALS00ADBR from Texas Instruments, in a SSOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; Y = NOT(A AND B), high-level input voltage min 2 V, low-level max 0.8 V.
2 1B input Gate 1 input B; Y = NOT(A AND B), high-level input voltage min 2 V, low-level max 0.8 V.
3 1Y output Gate 1 output, low only when 1A and 1B are both high; IOH -0.4 mA, IOL 8 mA (SN74ALS00A).
4 2A input Gate 2 input A; high-level input voltage min 2 V, low-level max 0.8 V.
5 2B input Gate 2 input B; high-level input voltage min 2 V, low-level max 0.8 V.
6 2Y output Gate 2 output, low only when 2A and 2B are both high; IOH -0.4 mA, IOL 8 mA (SN74ALS00A).
7 GND power_in Ground reference (0 V).
8 3Y output Gate 3 output, low only when 3A and 3B are both high; IOH -0.4 mA, IOL 8 mA (SN74ALS00A).
9 3A input Gate 3 input A; high-level input voltage min 2 V, low-level max 0.8 V.
10 3B input Gate 3 input B; high-level input voltage min 2 V, low-level max 0.8 V.
11 4Y output Gate 4 output, low only when 4A and 4B are both high; IOH -0.4 mA, IOL 8 mA (SN74ALS00A).
12 4A input Gate 4 input A; high-level input voltage min 2 V, low-level max 0.8 V.
13 4B input Gate 4 input B; high-level input voltage min 2 V, low-level max 0.8 V.
14 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), 7 V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-14-208mil
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74ALS00ADBR
  • Footprint: Package_SO:SSOP-14_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-14-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74als00adbr-etched.step / sn74als00adbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als00adbr.step / sn74als00adbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 727b9553ff7c7747, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF