LT3973EDD-3.3#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUT	input	For the LT3973-3.3 this pin is VOUT, which the internal feedback divider regulates to 3.3V and which connects to the fixed-output feedback divider.
2	OUT	input	OUT supplies dropout regulation between VIN and VOUT and pulls current to charge the boost capacitor, and must be tied to the output, or to GND if the programmed output is greater than 14V.
3	EN/UVLO	input	The part is in shutdown when EN/UVLO is low and active when high, with a threshold of 1.19V rising and 30mV hysteresis, and it is accurate only when VIN is above 4.2V.
4	VIN	power_in	VIN supplies the internal circuitry and power switch, must be locally bypassed, and has an absolute maximum of 42V.
5	GND	power_in	GND is the ground reference pin and must be connected to the exposed pad, which must be soldered to the PCB.
6	SW	output	SW is the output of the internal power switch and connects to the inductor.
7	BOOST	passive	BOOST provides a drive voltage higher than VIN to the internal NPN power switch and is limited to 55V absolute maximum.
8	BD	power_in	BD connects to the anode of the boost diode, supplies the internal regulator when above 3.2V, and has an absolute maximum of 25V.
9	PG	output	PG is the open-drain power good output that stays low until FB/VOUT is within 10% of the regulation voltage and is valid when VIN is above 4.2V and EN/UVLO is high.
10	RT	passive	A resistor from RT to ground sets the switching frequency, with the oscillator range stated as 200kHz to 2.2MHz.
11	GND	power_in	The exposed pad is ground and must be soldered to the PCB for thermal and electrical connection.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	DFN-10-EP(3x3)
Category	Power Management ICs
Pins	11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output voltage (LT3973-3.3)	VOUT	3.26	3.3	3.34	V		3
Output voltage over full operating temperature range (LT3973-3.3)	VOUT	3.234	3.3	3.366	V	l: full operating temperature range	3
Minimum input voltage	VIN	3.8		4.2	V	l: full operating temperature range	3
Quiescent current from VIN, EN/UVLO low	IQ		0.75	1.3	µA	VEN/UVLO Low	3
Quiescent current from VIN, EN/UVLO high	IQ		1.8	2.8	µA	VEN/UVLO High	3
Quiescent current from VIN, EN/UVLO high, -40°C to 125°C	IQ			6	µA	VEN/UVLO High, -40°C to 125°C	3
Quiescent current from VIN, EN/UVLO high, -40°C to 150°C	IQ			12	µA	VEN/UVLO High, -40°C to 150°C	3
FB/Output voltage line regulation			0.0002	0.01	%/V	4.2V < VIN < 40V	3
Switching frequency	fSW	1.72	2.15	2.58	MHz	RT = 41.2k, VIN = 6V	3
Switching frequency	fSW	632	790	948	kHz	RT = 158k, VIN = 6V	3
Switching frequency	fSW	156	195	234	kHz	RT = 768k, VIN = 6V	3
Switch current limit	ILIM	1.237	1.65	1.98	A	VIN = 5V, VFB = 0V, l	3
Catch Schottky current limit		0.92	1.15	1.44	A	VIN = 5V, l	3
Switch VCESAT	VCESAT			250	mV	ISW = 500mA	3
Switch leakage current			0.05	2	µA		3
Catch Schottky reverse leakage			0.05	2	µA	VSW = 12V	3
Boost Schottky reverse leakage			0.02	2	µA	VREVERSE = 12V	3
Minimum boost voltage		1.4		1.8	V	VIN = 5V, l	3
BOOST pin current			10	13	mA	ISW = 500mA, VBOOST = 15V	3
Dropout comparator threshold (VIN - OUT)		400	490	580	mV	Falling, VIN = 5V, l	3
Dropout comparator hysteresis			40		mV		3
EN/UVLO pin current			1	30	nA	VEN/UVLO = 12V	4
EN/UVLO voltage threshold, falling		1.09	1.16	1.23	V	EN/UVLO Falling, VIN ≥ 4.2V, l	4
EN/UVLO voltage threshold, rising		1.12	1.19	1.28	V	EN/UVLO Rising, VIN ≥ 4.2V, l	4
EN/UVLO voltage hysteresis			30	45	mV		4
PG threshold offset from feedback voltage		6.5	10	13.5	%	VFB rising	4
PG leakage			0.01	1	µA	VPG = 3V	4
PG sink current		220		350	µA	VPG = 0.4V, l	4
Minimum switch off-time			130	180	ns	VIN = 10V	4
Thermal resistance, junction to ambient (DD package)	θJA		40		°C/W	DD package (10-lead 3mm x 3mm DFN)	2
Thermal resistance, junction to case (DD package)	θJC		5		°C/W	DD package (10-lead 3mm x 3mm DFN)	2
Operating junction temperature range (E grade)	TJ	-40		125	°C	LT3973E/LT3973E-X	2
BOOST pin above SW pin				25	V		2
FB/VOUT, RT, PG voltage				6	V		2
BD voltage	VBD			25	V		2
Storage temperature range	TSTG	-65		150	°C		2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	ABS		LT3973HMSE-5#PBF LT3973HMSE-5#TRPBF LTGGD 10-Lead Plastic MSOP -40°C to 150°C ABSOLUTE MAXIMUM RATINGS	2

CAD (KiCad official)

Symbol: LT3973EDD-3.3#PBF
Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
3D model files: lt3973edd-3-3-pbf-etched.step / lt3973edd-3-3-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3973edd-3-3-pbf.step / lt3973edd-3-3-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 8b84083bfbac6278, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LT3973EDD-3.3#PBF

Verified LT3973EDD-3.3#PBF

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README