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XD74LS51

Public Made by Adom

by adom

XINLUDA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XD74LS51

XINLUDA · Logic Gates · DIP-14

XD74LS51 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A, one of the three inputs of the first AND term in 1Y = !((1A·1B·1C)+(1D·1E·1F)).
2 2A input Gate 2 input A, part of the first AND term in 2Y = !((2A·2B)+(2C·2D)).
3 2B input Gate 2 input B, part of the first AND term in 2Y = !((2A·2B)+(2C·2D)).
4 2C input Gate 2 input C, part of the second AND term in 2Y = !((2A·2B)+(2C·2D)).
5 2D input Gate 2 input D, part of the second AND term in 2Y = !((2A·2B)+(2C·2D)).
6 2Y output Gate 2 AND-OR-INVERT output, 2Y = !((2A·2B)+(2C·2D)).
7 GND power_in Ground, the reference for the voltage values in the ratings.
8 1Y output Gate 1 AND-OR-INVERT output, 1Y = !((1A·1B·1C)+(1D·1E·1F)).
9 1D input Gate 1 input D, one of the three inputs of the second AND term in 1Y.
10 1E input Gate 1 input E, one of the three inputs of the second AND term in 1Y.
11 1F input Gate 1 input F, one of the three inputs of the second AND term in 1Y.
12 1B input Gate 1 input B, one of the three inputs of the first AND term in 1Y.
13 1C input Gate 1 input C, one of the three inputs of the first AND term in 1Y.
14 VCC power_in Supply voltage, 4.75 V to 5.25 V recommended (5 V nominal), 7 V absolute maximum.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V see Note 1 (voltages with respect to network ground) 3
Input voltage (74LS51) VI 7 V 74LS51 3
Operating free-air temperature range (DIP package) 0 70 C DIP package 3
Storage temperature range Tstg -65 150 C 3
Supply voltage VCC 4.75 5 5.25 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -0.4 mA 4
Low-level output current IOL 8 mA 4
Operating free-air temperature TA 0 70 C 4
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = −0.4 mA 4
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 4
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 4
High-level input current IIH 20 μA VCC = MAX, VI = 2.7 V 4
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -20 -100 mA VCC = MAX 4
Supply current, outputs high ICCH 0.8 1.6 mA VCC = MAX, VI = 4.5 V 4
Supply current, outputs low ICCL 1.4 2.8 mA VCC = MAX, VI = 0 V 4
Propagation delay, low-to-high level output tPLH 12 20 ns RL = 2 kΩ, CL = 15 pF 4
Propagation delay, high-to-low level output tPHL 12.5 20 ns RL = 2 kΩ, CL = 15 pF 4

CAD (KiCad official)

  • Symbol: XD74LS51
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls51-etched.step / xd74ls51-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls51.step / xd74ls51.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 5536eabebe5932c6, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF