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TLV62569PDDCR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOT-23-THIN-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

markdown

TLV62569PDDCR

Texas Instruments · DC-DC Converters · SOT-23-THIN-6

TLV62569PDDCR from Texas Instruments, in a SOT-23-THIN-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Device enable logic input. Logic high enables the converter; logic low disables the device and puts it into shutdown. Do not leave floating. VIH ≥ 0.95 V (typ), VIL ≤ 0.85 V (typ), absolute max 6 V.
2 GND power_in Ground pin. Reference for all voltages; also serves as return for the internal low-side FET.
3 SW power_out Switch pin connected to the internal high-side and low-side FET switches and the inductor terminal. Connect the inductor of the output filter to this pin. DC range −0.3 V to VIN+0.3 V; AC (<10 ns) −3.0 V to 9 V.
4 VIN power_in Power supply voltage input. Operating range 2.5 V to 5.5 V; absolute max 6 V. Bypass locally to GND with a low-ESR ceramic capacitor.
5 PG output Power Good open-drain output (TLV62569P only). Asserts high (via external pull-up) when VFB is within regulation. External pull-up must not exceed 5.5 V; IPG sink capability 1 mA at VPG,OL ≤ 0.4 V. Leave floating if unused.
6 FB input Feedback pin for the internal control loop. Connect to the mid-point of an external resistor divider from VOUT to GND. Regulation target VFB = 0.6 V (typ, 0.588-0.612 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-THIN-6
Category PMIC
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • TLV62569PDDCR
  • TLV62569PDDCT
  • TLV62569PDDCRDBV
  • TLV62569PDDCRDBVR
  • TLV62569PDDCRDBVT
  • TLV62569PDDCRDRLR
  • TLV62569PDDCRPDRLR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage at VIN, EN, PG VIN, EN, PG -0.3 6 V 3
Voltage at SW (DC) SW -0.3 V DC; max printed as VIN+0.3 3
Voltage at SW (AC) SW -3 9 V AC, less than 10 ns 3
Voltage at FB FB -0.3 5.5 V 3
Operating junction temperature TJ -40 150 °C 3
Storage temperature Tstg -65 150 °C 3
Input voltage VIN 2.5 5.5 V 4
Output voltage VOUT 0.6 V max printed as VIN 4
Output current IOUT 0 2 A 4
Operating junction temperature TJ -40 125 °C 4
Sink current at PG pin ISINK_PG 1 mA 4
Quiescent current into VIN pin IQ 35 uA Not switching 4
Shutdown current into VIN pin ISD 0.1 2 µA EN = 0 V 4
Under voltage lock out (falling) VUVLO 2.3 2.45 V VIN falling 4
Under voltage lock out hysteresis VUVLO 100 mV 4
Thermal shutdown (rising) TJSD 150 °C Junction temperature rising 4
Thermal shutdown (falling) TJSD 130 °C Junction temperature falling 4
High-level threshold at EN pin VIH 0.95 1.2 V 2.5 V ≤ VIN ≤ 5.5 V 4
Low-level threshold at EN pin VIL 0.4 0.85 V 2.5 V ≤ VIN ≤ 5.5 V 4
Soft startup time (TLV62569PDDC) tSS 900 µs TLV62569PDDC 4
Power good threshold (rising) VPG 95 % VFB rising, referenced to VFB nominal 4
Power good threshold (falling) VPG 90 % VFB falling, referenced to VFB nominal 4
Power good low-level output voltage VPG,OL 0.4 V ISINK = 1 mA 4
Input leakage current into PG pin IPG,LKG 0.01 µA VPG = 5.0 V 4
Power good delay time tPG,DLY 40 µs VFB falling 4
Feedback regulation voltage VFB 0.588 0.6 0.612 V 4
High-side FET on resistance RDS(on) 100 mΩ 5
Low-side FET on resistance RDS(on) 60 mΩ 5
High-side FET current limit (TLV62569PDDC) ILIM 3 A TLV62569PDDC 5
Switching frequency fSW 1.5 MHz VOUT = 2.5 V 5
Junction-to-ambient thermal resistance RθJA 106.2 °C/W DDC (6 pins) 4
Junction-to-case (top) thermal resistance RθJC(top) 52.9 °C/W DDC (6 pins) 4
Junction-to-board thermal resistance RθJB 31.2 °C/W DDC (6 pins) 4
Junction-to-top characterization parameter ψJT 11.3 °C/W DDC (6 pins) 4
Junction-to-board characterization parameter ψJB 31.6 °C/W DDC (6 pins) 4

CAD (KiCad official)

  • Symbol: TLV62569PDDCR
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23-THIN-6 (KiCad packages3D, STEP)
  • 3D model files: tlv62569pddcr-etched.step / tlv62569pddcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv62569pddcr.step / tlv62569pddcr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tlv62569pddcr.step 97 KB You want the bare part, or you mark your own boards.
tlv62569pddcr-etched.step 2.4 MB You want the part with TLV62569PDDCR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 578 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 2fb0ac3bf691ff6e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF