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MSPM0G1505SRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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MSPM0G1505SRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSPM0G1505SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5 V-tolerant open-drain GPIO (ODIO) with no PMOS driver, so it needs an external pull-up to output high; it can wake the device from SHUTDOWN.
2 PA1 bidirectional 5 V-tolerant open-drain GPIO (ODIO) with no PMOS driver, so it needs an external pull-up to output high; it can wake the device from SHUTDOWN.
3 PA28 bidirectional High-drive GPIO (HDIO) rated for 20 mA sink/source; it can wake the device from SHUTDOWN.
4 NRST input Active-low reset input that must be pulled up to VDD for the device to leave reset and start.
5 PA31 bidirectional High-drive GPIO (HDIO) rated for 20 mA sink/source; it can wake the device from SHUTDOWN; alternate function CLK_OUT.
6 VDD power_in Power supply; recommended operating range 1.62 V to 3.6 V, with 10 µF and 0.1 µF decoupling to VSS placed within a few millimetres of the pin.
7 VSS power_in Ground reference for the device.
8 PA2 bidirectional Standard GPIO; this pin is the ROSC input for the 100 kΩ ±0.1% reference resistor used by the SYSOSC frequency correction loop, and it is free as GPIO only when that loop is not used.
9 PA3 bidirectional Standard GPIO; alternate function LFXIN, the input of the 32 kHz low-frequency crystal oscillator.
10 PA4 bidirectional Standard GPIO; alternate functions LFXOUT (32 kHz crystal output) or LFCLK_IN (digital 32.768 kHz clock input).
11 PA5 bidirectional Standard GPIO; alternate function HFXIN, the input of the 4 MHz to 48 MHz high-frequency crystal oscillator.
12 PA6 bidirectional Standard GPIO; alternate functions HFXOUT (high-frequency crystal output) or HFCLK_IN (digital clock input, 4 MHz to 48 MHz).
13 PA7 bidirectional Standard GPIO; alternate functions include CLK_OUT and COMP0_OUT.
14 PB2 bidirectional Standard GPIO; alternate functions include UART3_TX and I2C1_SCL.
15 PB3 bidirectional Standard GPIO; alternate functions include UART3_RX and I2C1_SDA.
16 PA8 bidirectional Standard GPIO; alternate functions include UART1_TX and SPI0_CS0.
17 PA9 bidirectional High-speed GPIO (HSIO); alternate functions include RTC_OUT and CLK_OUT; port output frequency up to 40 MHz at VDD ≥ 2.7 V with DRV = 1.
18 PA10 bidirectional High-drive GPIO (HDIO) rated for 20 mA sink/source; default BSL UART transmit (BSLTX) and alternate function UART0_TX.
19 PA11 bidirectional High-drive GPIO (HDIO) rated for 20 mA sink/source; default BSL UART receive (BSLRX) and alternate function UART0_RX; can wake the device from SHUTDOWN.
20 PB6 bidirectional Standard GPIO; alternate functions include UART1_TX and SPI1_CS0.
21 PB7 bidirectional Standard GPIO; alternate functions include UART1_RX and SPI1_POCI.
22 PB8 bidirectional Standard GPIO; alternate functions include UART1_CTS and SPI1_PICO.
23 PB9 bidirectional Standard GPIO; alternate functions include UART1_RTS and SPI1_SCK.
24 PB14 bidirectional Standard GPIO; alternate functions include SPI1_CS3 and SPI1_POCI.
25 PB15 bidirectional Standard GPIO; alternate functions include UART2_TX and SPI1_PICO.
26 PB16 bidirectional Standard GPIO; alternate functions include UART2_RX and SPI1_SCK.
27 PA12 bidirectional High-speed GPIO (HSIO); alternate functions include UART3_CTS, SPI0_SCK and FCC_IN.
28 PA13 bidirectional High-speed GPIO (HSIO); also COMP0_IN2- analog input; alternate functions include UART3_RTS and SPI0_POCI.
29 PA14 bidirectional High-speed GPIO (HSIO); also ADC0 analog input A0_12 and COMP0_IN2+; alternate functions include UART0_CTS and CLK_OUT.
30 PA15 bidirectional Standard GPIO; also ADC1 analog input A1_0 and DAC_OUT; when DAC_OUT is enabled, no external signal should be connected to this pin.
31 PA16 bidirectional Standard GPIO; also ADC1 analog input A1_1 and OPA1_OUT; alternate function COMP2_OUT.
32 PA17 bidirectional Standard GPIO with wake-up capability from SHUTDOWN; also ADC1 analog input A1_2 and OPA1_IN1-/COMP0_IN1-.
33 PA18 bidirectional Standard GPIO with wake-up capability from SHUTDOWN; also ADC1 analog input A1_3 and OPA1_IN1+/COMP0_IN1+/GPAMP_IN-.
34 PA19 bidirectional High-speed GPIO (HSIO); default function SWDIO serial-wire debug data input/output.
35 PA20 bidirectional Standard GPIO; default function SWCLK serial-wire debug clock input from the debug probe.
36 PB17 bidirectional Standard GPIO; also ADC1 analog input A1_4 and COMP1_IN2-.
37 PB18 bidirectional Standard GPIO; also ADC1 analog input A1_5 and COMP1_IN2+.
38 PB19 bidirectional Standard GPIO; also ADC1 analog input A1_6, COMP2_IN1+ and OPA1_IN0+.
39 PA21 bidirectional Standard GPIO; also ADC1 analog input A1_7, COMP2_IN1- and the VREF- pin.
40 PA22 bidirectional Standard GPIO; also ADC0 analog input A0_7, GPAMP_OUT and OPA0_OUT.
41 PB20 bidirectional Standard GPIO; also ADC0 analog input A0_6 and OPA1_IN0-.
42 PB24 bidirectional Standard GPIO; also ADC0 analog input A0_5 and COMP1_IN1+.
43 PA23 bidirectional Standard GPIO; also the VREF+ external voltage reference input/internal reference output and COMP1_IN1-.
44 PA24 bidirectional Standard GPIO; also ADC0 analog input A0_3 and OPA0_IN1-.
45 PA25 bidirectional Standard GPIO; also ADC0 analog input A0_2 and OPA0_IN1+.
46 PA26 bidirectional Standard GPIO; also ADC0 analog input A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+.
47 PA27 bidirectional Standard GPIO; also ADC0 analog input A0_0, COMP0_IN0-, OPA0_IN0- and RTC_OUT alternate function.
48 VCORE power_out Regulated core supply output: connect only a 470 nF low-ESR capacitor between VCORE and VSS placed close to the pin; do not apply any voltage or external load to it.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSPM0G1505SRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1505srgzr-etched.step / mspm0g1505srgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1505srgzr.step / mspm0g1505srgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 5fe0f52106449460, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF