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AVR64DA32-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr64da32-ifactory-2.0.0extractor-text

Verified AVR64DA32-I

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 32 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR64DA32-I · TQFP-32(7x7) · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 684-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-32_7x7mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-53aub4ih/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr64da32-i.kicad_sym✓ avr64da32-i.kicad_mod✓ avr64da32-i.step
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Symbol & Footprint

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Contents

README

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AVR64DA32-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-32(7x7)

AVR64DA32-I from Microchip Tech, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin PA3 on PORTA with alternate functions TWI SCL (host), USART0 XDIR, TCA0 WO3, ADC0 X3/Y3 and CCL LUT0 OUT, selectable via PORTMUX.
2 PA4 bidirectional General-purpose I/O pin PA4 on PORTA with alternate functions USART0 TxD, SPI0 MOSI, TCA0 WO4 and ADC0 X4/Y4.
3 PA5 bidirectional General-purpose I/O pin PA5 on PORTA with alternate functions USART0 RxD, SPI0 MISO, TCA0 WO5 and ADC0 X5/Y5.
4 PA6 bidirectional General-purpose I/O pin PA6 on PORTA with alternate functions USART0 XCK, SPI0 SCK, TCA0 WOC and ADC0 X6/Y6.
5 PA7 bidirectional General-purpose I/O pin PA7 on PORTA with alternate functions CLKOUT, USART0 XDIR, SPI0 SS, TCA0 WOD, EVSYS EVOUTA and ADC0 X7/Y7.
6 PC0 bidirectional General-purpose I/O pin PC0 on PORTC with alternate functions USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 and ADC0 functions.
7 PC1 bidirectional General-purpose I/O pin PC1 on PORTC with alternate functions USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 and ADC0 functions.
8 PC2 bidirectional General-purpose I/O pin PC2 on PORTC with alternate functions TWI SDA (host), USART1 XCK, SPI0 SCK (alternate position), TCA0 WO2 and event output EVOUTC.
9 PC3 bidirectional General-purpose I/O pin PC3 on PORTC with alternate functions TWI SCL (host), USART1 XDIR, SPI0 SS (alternate position) and TCA0 WO3.
10 PD0 bidirectional General-purpose I/O pin PD0 on the analog-capable PORTD with ADC0 input AIN0 and alternate functions AC0 AINN1, TCA0 WO0 and event system.
11 PD1 bidirectional General-purpose I/O pin PD1 on the analog-capable PORTD with ADC0 input AIN1, analog comparator ZCIN function and TCA0 WO1.
12 PD2 bidirectional General-purpose I/O pin PD2 on the analog-capable PORTD with ADC0 input AIN2, AC0 AINP0 function, TCA0 WO2 and event output EVOUTD.
13 PD3 bidirectional General-purpose I/O pin PD3 on the analog-capable PORTD with ADC0 input AIN3, AC0 AINN0 function and TCA0 WO3.
14 PD4 bidirectional General-purpose I/O pin PD4 on the analog-capable PORTD with ADC0 input AIN4, AC1 AINP function and TCA0 WO4.
15 PD5 bidirectional General-purpose I/O pin PD5 on the analog-capable PORTD with ADC0 input AIN5, AC1 AINN function and TCA0 WO5.
16 PD6 bidirectional General-purpose I/O pin PD6 on the analog-capable PORTD with ADC0 input AIN6, AC0 AINP3 function and DAC0 VOUT.
17 PD7 bidirectional General-purpose I/O pin PD7 on the analog-capable PORTD with VREFA external voltage reference input, ADC0 input AIN7 and event output EVOUTD.
18 AVDD power_in Analog supply pin for the AVDD power domain; on this device AVDD and VDD are internally connected.
19 GND power_in Ground reference pin; it must be connected to the ground plane with a decoupling capacitor placed close to the supply pin pair.
20 PF0 bidirectional General-purpose I/O pin PF0 that doubles as crystal pin XTAL32K1 and ADC0 positive input AIN16 (positive input-only).
21 PF1 bidirectional General-purpose I/O pin PF1 that doubles as crystal pin XTAL32K2 and ADC0 positive input AIN17 (positive input-only).
22 PF2 bidirectional General-purpose I/O pin PF2 with alternate functions TWI, USART2 XCK, TCA0 WO2 and event output EVOUTF, plus ADC0 positive input AIN18.
23 PF3 bidirectional General-purpose I/O pin PF3 with alternate functions TWI SCL (host), USART2 XDIR, TCA0 WO3 and ADC0 positive input AIN19.
24 PF4 bidirectional General-purpose I/O pin PF4 with alternate functions USART2 TxD, TCA0 WO4 and ADC0 positive input AIN20.
25 PF5 bidirectional General-purpose I/O pin PF5 with alternate functions USART2 RxD, TCA0 WO5 and ADC0 positive input AIN21.
26 PF6 input Input-only pin PF6 that is the external RESET pin when RSTPINCFG selects RESET; the RESET pin is active-low with an internal pull-up.
27 UPDI bidirectional Dedicated Unified Program and Debug Interface pin used for one-wire UART programming and debugging; it has no other function.
28 VDD power_in Digital supply pin; all VDD pins are internally connected and the same voltage must be applied to each of them.
29 GND power_in Ground reference pin; it must be connected to the ground plane with a decoupling capacitor placed close to the supply pin pair.
30 PA0 bidirectional General-purpose I/O pin PA0 that is the EXTCLK external clock input with alternate functions USART0 TxD, TCA0 WO0 and ADC0 X0/Y0.
31 PA1 bidirectional General-purpose I/O pin PA1 with alternate functions USART0 RxD, TCA0 WO1 and ADC0 X1/Y1.
32 PA2 bidirectional General-purpose I/O pin PA2 with alternate functions TWI SDA (host), USART0 XCK, TCA0 WO2, event output EVOUTA and ADC0 X2/Y2.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-32(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 32

CAD (KiCad official)

  • Symbol: AVR64DA32-I
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: avr64da32-i-etched.step / avr64da32-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr64da32-i.step / avr64da32-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (684 pp, sha256 42c2071125f65ca1, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF