component

ADS4149IRGZR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADCs), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionads4149irgzrfactory-2.0.0extractor-text

Verified ADS4149IRGZR

by Ray · last 10 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

10 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS4149IRGZR · QFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 83-page datasheet
  • ✓distributor: lcsc C2670820, digikey ADS4149IRGZR-ND, mouser 595-ADS4149IRGZR
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-do_hlci_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads4149irgzr.kicad_sym✓ ads4149irgzr.kicad_mod✓ ads4149irgzr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ADS4149IRGZR

Texas Instruments · Analog To Digital Converters (ADCs) · QFN-48-EP(7x7)

ADS4149IRGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRGND power_in Digital and output buffer ground.
2 DRVDD power_in 1.8V digital and output buffer supply.
3 OVR_SDOUT output Out-of-range indicator after reset when READOUT = 0, and serial register readout pin when READOUT = 1.
4 CLKOUTM output Differential output clock, complement.
5 CLKOUTP output Differential output clock, true.
6 DFS input Analog 4-level data format select input that sets twos complement or offset binary and the LVDS/CMOS output interface type.
7 OE input Output buffer enable input, active high, with internal 180kΩ pull-up resistor to DRVDD.
8 AVDD power_in 1.8V analog power supply.
9 AGND power_in Analog ground.
10 CLKP input Differential clock input, positive.
11 CLKM input Differential clock input, negative.
12 AGND power_in Analog ground.
13 VCM output Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins.
14 AGND power_in Analog ground.
15 INP input Differential analog input, positive.
16 INM input Differential analog input, negative.
17 AGND power_in Analog ground.
18 AVDD power_in 1.8V analog power supply.
19 AGND power_in Analog ground.
20 AVDD power_in 1.8V analog power supply.
21 NC unconnected Do not connect.
22 AVDD power_in 1.8V analog power supply.
23 RESERVED input Digital control pin, reserved for future use.
24 AVDD power_in 1.8V analog power supply.
25 AGND power_in Analog ground.
26 AVDD power_in 1.8V analog power supply.
27 SEN input Serial interface enable input when RESET is low; when RESET is high it has no function and should be tied to AVDD; internal 180kΩ pull-up to AVDD.
28 SDATA input Serial interface data input when RESET is low; when RESET is high it functions as STANDBY control; internal 180kΩ pull-down resistor.
29 SCLK input Serial interface clock input when RESET is low; when RESET is high it has no function and should be tied to ground; internal 180kΩ pull-down resistor.
30 RESET input Serial interface reset input; a high pulse initializes the internal registers, and when tied high the registers are at defaults and SEN can be an analog control pin; internal 180kΩ pull-down resistor.
31 NC unconnected Do not connect.
32 NC unconnected Do not connect.
33 D0_D1_M output Differential output data D0 and D1 multiplexed, complement.
34 D0_D1_P output Differential output data D0 and D1 multiplexed, true.
35 DRVDD power_in 1.8V digital and output buffer supply.
36 DRGND power_in Digital and output buffer ground.
37 D2_D3_M output Differential output data D2 and D3 multiplexed, complement.
38 D2_D3_P output Differential output data D2 and D3 multiplexed, true.
39 D4_D5_M output Differential output data D4 and D5 multiplexed, complement.
40 D4_D5_P output Differential output data D4 and D5 multiplexed, true.
41 D6_D7_M output Differential output data D6 and D7 multiplexed, complement.
42 D6_D7_P output Differential output data D6 and D7 multiplexed, true.
43 D8_D9_M output Differential output data D8 and D9 multiplexed, complement.
44 D8_D9_P output Differential output data D8 and D9 multiplexed, true.
45 D10_D11_M output Differential output data D10 and D11 multiplexed, complement.
46 D10_D11_P output Differential output data D10 and D11 multiplexed, true.
47 D12_D13_M output Differential output data D12 and D13 multiplexed, complement.
48 D12_D13_P output Differential output data D12 and D13 multiplexed, true.
49 PAD power_in PowerPAD exposed thermal pad, connected to DRGND (digital and output buffer ground).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category ADC/DAC/Data Conversion
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range, AVDD AVDD -0.3 2.1 V 3
Supply voltage range, DRVDD DRVDD -0.3 2.1 V 3
Voltage between AGND and DRGND -0.3 0.3 V 3
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 2.1 V 3
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) 0 2.1 V 3
Voltage applied to RESET, SCLK, SDATA, SEN -0.3 3.9 V 3
Operating free-air temperature range, TA TA -40 85 °C 3
Operating junction temperature range, TJ TJ 125 °C 3
Storage temperature range, Tstg Tstg -65 150 °C 3
ESD, human body model (HBM) 2 kV 3
Analog supply voltage AVDD 1.7 1.8 1.9 V 4
Digital supply voltage DRVDD 1.7 1.8 1.9 V 4
Input common-mode voltage (VCM ± 0.05) VCM -0.05 0.05 V 4
Maximum analog input frequency with 2VPP input amplitude 400 MHz 2VPP input amplitude 4
Maximum analog input frequency with 1VPP input amplitude 800 MHz 1VPP input amplitude 4
Input clock sample rate, low-speed mode enabled 20 80 MSPS ADS4129/ADS4149, low-speed mode enabled 4
Input clock sample rate, low-speed mode disabled 80 250 MSPS ADS4129/ADS4149, low-speed mode disabled; printed as >80 4
Input clock amplitude differential, sine wave ac-coupled 0.2 1.5 VPP Sine wave, ac-coupled 4
Input clock amplitude differential, LVPECL ac-coupled 1.6 VPP LVPECL, ac-coupled 4
Input clock amplitude differential, LVDS ac-coupled 0.7 VPP LVDS, ac-coupled 4
Input clock amplitude, LVCMOS single-ended ac-coupled 1.8 V LVCMOS, single-ended, ac-coupled 4
Input clock duty cycle, low-speed mode enabled 40 50 60 % Low-speed mode enabled 4
Input clock duty cycle, low-speed mode disabled 35 50 65 % Low-speed mode disabled 4
Maximum external load capacitance from each output pin to DRGND CLOAD 5 pF 4
Signal-to-noise ratio, LVDS, fIN = 170MHz SNR 67.5 70.6 dBFS fIN = 170MHz, LVDS 6
Signal-to-noise and distortion ratio, LVDS, fIN = 170MHz SINAD 66 69.4 dBFS fIN = 170MHz, LVDS 6
Spurious-free dynamic range, fIN = 170MHz SFDR 72 84 dBc fIN = 170MHz 6
Total harmonic distortion, fIN = 170MHz THD 71 80.5 dBc fIN = 170MHz 6
Second-harmonic distortion, fIN = 170MHz HD2 72 84 dBc fIN = 170MHz 6
Third-harmonic distortion, fIN = 170MHz HD3 72 82 dBc fIN = 170MHz 6
Worst spur (other than second and third harmonics), fIN = 170MHz 77 88 dBc fIN = 170MHz 6
Differential nonlinearity, fIN = 170MHz DNL -0.95 LSBs fIN = 170MHz 6
Integrated nonlinearity, fIN = 170MHz INL 5 LSBs fIN = 170MHz 6
Differential input resistance (at dc) 1 MΩ at dc; see Figure 114 7
Offset error -15 2.5 15 mV 7
Gain error as a result of internal reference inaccuracy alone EGREF -2 2 %FS 7
Global power-down 10 25 mW Global power-down mode 7
High-level input voltage, RESET, SCLK, SDATA, and SEN 1.3 V SEN supports 1.8V and 3.3V 8
Low-level input voltage 0.4 V CMOS logic levels 8
High-level input voltage, OE 1.3 V OE only supports 1.8V CMOS logic levels 8
Low-level input voltage, OE 0.4 V OE only supports 1.8V CMOS logic levels 8
Low-level output voltage, CMOS interface 0 0.1 V 8
High-level output voltage, standard swing LVDS VODH 270 350 430 mV Standard swing LVDS, with external 100Ω termination 8
Low-level output voltage, standard swing LVDS VODL -430 -350 -270 mV Standard swing LVDS, with external 100Ω termination 8
Output common-mode voltage VOCM 0.85 1.05 1.25 V 8
Aperture delay tA 0.6 0.8 1.2 ns 17
Clock propagation delay, DDR LVDS mode tPDI 3 4.2 5.4 ns 1MSPS ≤ sampling frequency ≤ 250MSPS 17
LVDS bit clock duty cycle, CLKOUTP-CLKOUTM 42 48 54 % 1MSPS ≤ sampling frequency ≤ 250MSPS 18
Clock propagation delay, parallel CMOS mode tPDI 4 5.5 7 ns 1MSPS ≤ sampling frequency ≤ 200MSPS 18
SCLK frequency fSCLK 20 MHz 23
Junction-to-ambient thermal resistance θJA 29 °C/W RGZ 48 pins 3
Junction-to-board thermal resistance θJB 10 °C/W RGZ 48 pins 3
Junction-to-case (bottom) thermal resistance θJCbot 1.13 °C/W RGZ 48 pins 3
Junction-to-top characterization parameter ψJT 0.3 °C/W RGZ 48 pins 3
Junction-to-board characterization parameter ψJB 9 °C/W RGZ 48 pins 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs ESD, human body model (HBM) 2 kV (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may 3

CAD (KiCad official)

  • Symbol: ADS4149IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads4149irgzr-etched.step / ads4149irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4149irgzr.step / ads4149irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (83 pp, sha256 74c5b7c59136a967, retrieved 2026-11-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF