component
PUMH11F
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPUMH11F
Nexperia · Digital Transistors · SOT-363
PUMH11F from Nexperia, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND1 | power_in | Emitter of TR1, the ground reference for the TR1 input and output; Table 2 gives no pin-specific electrical limit. |
| 2 | I1 | input | Base input of TR1 through built-in bias resistor R1 (10 kΩ typical, 7 to 13 kΩ); the per-transistor input voltage limits are 40 V positive and -10 V negative. |
| 3 | O2 | output | Collector output of TR2; per-transistor limits are VCEO 50 V and output current 100 mA. |
| 4 | GND2 | power_in | Emitter of TR2, the ground reference for the TR2 input and output; Table 2 gives no pin-specific electrical limit. |
| 5 | I2 | input | Base input of TR2 through built-in bias resistor R2 (10 kΩ typical, with R2/R1 ratio 0.8 to 1.2); the per-transistor input voltage limits are 40 V positive and -10 V negative. |
| 6 | O1 | output | Collector output of TR1; per-transistor limits are VCEO 50 V and output current 100 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-base voltage | VCBO | 50 | V | open emitter; per transistor | 3 | ||
| Collector-emitter voltage | VCEO | 50 | V | open base; per transistor | 3 | ||
| Emitter-base voltage | VEBO | 10 | V | open collector; per transistor | 3 | ||
| Input voltage (positive) | VI | 40 | V | positive; per transistor | 3 | ||
| Input voltage (negative) | VI | -10 | V | negative; per transistor | 3 | ||
| Output current | IO | 100 | mA | per transistor | 3 | ||
| Total power dissipation (per transistor) | Ptot | 200 | mW | Tamb ≤ 25 °C; device mounted on FR4 PCB, single-sided, 35 μm copper | 3 | ||
| Total power dissipation (per device) | Ptot | 300 | mW | Tamb = 25 °C; device mounted on FR4 PCB, single-sided, 35 μm copper | 3 | ||
| Junction temperature | Tj | 150 | °C | 3 | |||
| Ambient temperature | Tamb | -65 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Thermal resistance junction to ambient (per transistor) | Rth(j-a) | 625 | K/W | in free air; device mounted on FR4 PCB, single-sided, 35 μm copper | 4 | ||
| Thermal resistance junction to ambient (per device) | Rth(j-a) | 417 | K/W | in free air; device mounted on FR4 PCB, single-sided, 35 μm copper | 4 | ||
| Collector-base breakdown voltage | V(BR)CBO | 50 | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C | 5 | ||
| Collector-emitter breakdown voltage | V(BR)CEO | 50 | V | IC = 2 mA; IB = 0 A; Tamb = 25 °C | 5 | ||
| Collector-base cut-off current | ICBO | 100 | nA | VCB = 50 V; IE = 0 A | 5 | ||
| Collector-emitter cut-off current | ICEO | 1 | µA | VCE = 30 V; IB = 0 A | 5 | ||
| Collector-emitter cut-off current | ICEO | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 5 | ||
| Emitter-base cut-off current | IEBO | 400 | µA | VEB = 5 V; IC = 0 A | 5 | ||
| DC current gain | hFE | 30 | VCE = 5 V; IC = 5 mA | 5 | |||
| Collector-emitter saturation voltage | VCEsat | 150 | mV | IC = 10 mA; IB = 0.5 mA | 5 | ||
| Off-state input voltage | VI(off) | 1.1 | 0.8 | V | VCE = 5 V; IC = 100 µA | 5 | |
| On-state input voltage | VI(on) | 2.5 | 1.8 | V | VCE = 0.3 V; IC = 10 mA | 5 | |
| Bias resistor 1 (input) | R1 | 7 | 10 | 13 | kΩ | 5 | |
| Bias resistor ratio | R2/R1 | 0.8 | 1 | 1.2 | 5 | ||
| Collector capacitance | Cc | 2.5 | pF | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz | 5 |
CAD (KiCad official)
- Symbol:
PUMH11F - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
pumh11f-etched.step/pumh11f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pumh11f.step/pumh11f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (11 pp, sha256
73f0cd37da41b7c8, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).