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ATSAMD21E18A-MUT
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownATSAMD21E18A-MUT
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-32-EP(5x5)
ATSAMD21E18A-MUT from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA00 | bidirectional | Port A I/O pin 0 on the VDDANA analog supply domain, also EXTINT[0] and the XIN32 32 kHz crystal input when XOSC32K is used. |
| 2 | PA01 | bidirectional | Port A I/O pin 1 on the VDDANA analog supply domain, also EXTINT[1] and the XOUT32 32 kHz crystal output when XOSC32K is used. |
| 3 | PA02 | bidirectional | Port A I/O pin 2 on the VDDANA analog supply domain, with analog input AIN[0], DAC output VOUT and EXTINT[2]. |
| 4 | PA03 | bidirectional | Port A I/O pin 3 on the VDDANA analog supply domain, with analog input AIN[1], EXTINT[3] and the ADC/DAC external reference VREFA. |
| 5 | PA04 | bidirectional | Port A I/O pin 4 on the VDDANA analog supply domain, with analog input AIN[4], EXTINT[4] and the ADC external reference VREFB. |
| 6 | PA05 | bidirectional | Port A I/O pin 5 on the VDDANA analog supply domain, with analog input AIN[5] and EXTINT[5]. |
| 7 | PA06 | bidirectional | Port A I/O pin 6 on the VDDANA analog supply domain, with analog input AIN[6] and EXTINT[6]. |
| 8 | PA07 | bidirectional | Port A I/O pin 7 on the VDDANA analog supply domain, with analog input AIN[7] and EXTINT[7]. |
| 9 | VDDANA | power_in | Analog supply voltage for the analog power domain, specified at 1.62 V to 3.63 V for SAM D21 in the schematic checklist. |
| 10 | GND | power_in | Ground connection for the device. |
| 11 | PA08 | bidirectional | Port A I/O pin 8 on the VDDIO supply domain, with NMI, analog input AIN[16] and SERCOM0 PAD[0]; listed as an I2C Hs-capable pin. |
| 12 | PA09 | bidirectional | Port A I/O pin 9 on the VDDIO supply domain, with EXTINT[9], analog input AIN[17] and SERCOM0 PAD[1]; listed as an I2C Hs-capable pin. |
| 13 | PA10 | bidirectional | Port A I/O pin 10 on the VDDIO supply domain, with EXTINT[10], analog input AIN[18] and SERCOM0 PAD[2]. |
| 14 | PA11 | bidirectional | Port A I/O pin 11 on the VDDIO supply domain, with EXTINT[11], analog input AIN[19] and SERCOM0 PAD[3]. |
| 15 | PA14 | bidirectional | Port A I/O pin 14 on the VDDIO supply domain, with EXTINT[14]; it is also the XIN oscillator input when XOSC is used. |
| 16 | PA15 | bidirectional | Port A I/O pin 15 on the VDDIO supply domain, with EXTINT[15]; it is also the XOUT oscillator output when XOSC is used. |
| 17 | PA16 | bidirectional | Port A I/O pin 16 on the VDDIO supply domain, with EXTINT[0] and SERCOM1/SERCOM3 PAD[0] functions. |
| 18 | PA17 | bidirectional | Port A I/O pin 17 on the VDDIO supply domain, with EXTINT[1] and SERCOM1 PAD[1] functions. |
| 19 | PA18 | bidirectional | Port A I/O pin 18 on the VDDIO supply domain, with EXTINT[2] and SERCOM1 PAD[2] functions. |
| 20 | PA19 | bidirectional | Port A I/O pin 19 on the VDDIO supply domain, with EXTINT[3] and SERCOM1 PAD[3] functions. |
| 21 | PA22 | bidirectional | Port A I/O pin 22 on the VDDIO supply domain, with EXTINT[6] and SERCOM3 PAD[0] functions. |
| 22 | PA23 | bidirectional | Port A I/O pin 23 on the VDDIO supply domain, with EXTINT[7] and SERCOM3 PAD[1] functions. |
| 23 | PA24 | bidirectional | Port A I/O pin 24 on the VDDIO supply domain, with EXTINT[12] and USB DM; the datasheet recommends a pull-up through GPIO input mode if the pin is unconnected. |
| 24 | PA25 | bidirectional | Port A I/O pin 25 on the VDDIO supply domain, with EXTINT[13] and USB DP. |
| 25 | PA27 | bidirectional | Port A I/O pin 27 on the VDDIO supply domain, with EXTINT[15] and GCLK_IO[0]. |
| 26 | RESET | input | External active-low reset input with an internal pull-up; the low-level threshold is below 0.36 × VDDIO at 2.7 V to 3.6 V. |
| 27 | PA28 | bidirectional | Port A I/O pin 28 on the VDDIO supply domain, with EXTINT[8] and GCLK_IO[0]. |
| 28 | GND | power_in | Ground connection for the device. |
| 29 | VDDCORE | power_out | Core supply pin for the internal regulator output, to be decoupled with a 1 µF capacitor and specified at 1.6 V to 1.8 V. |
| 30 | VDDIN | power_in | Input supply pin for the device, part of the single 1.62 V to 3.63 V supply for SAM D21. |
| 31 | PA30 | bidirectional | Port A I/O pin 30 on the VDDIO supply domain, with EXTINT[10] and SWCLK, the Serial Wire Debug clock input. |
| 32 | PA31 | bidirectional | Port A I/O pin 31 on the VDDIO supply domain, with EXTINT[11] and SWDIO, the Serial Wire Debug data pin which is only active when a debugger is present. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (VDD, VDDIO/VDDIN/VDDANA) | VDD | 1.62 | 3.63 | V | SAM D21 variant; VDDIO, VDDIN and VDDANA must be the same voltage | 36 | |
| Operating temperature range (ordering grade U) | -40 | 85 | °C | Ordering suffix U = -40 - 85°C Matte Sn plating; MUT suffix = QFN, tape and reel | 17 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 860 |
CAD (KiCad official)
- Symbol:
ATSAMD21E18A-MUT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
atsamd21e18a-mut-etched.step/atsamd21e18a-mut-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsamd21e18a-mut.step/atsamd21e18a-mut.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1115 pp, sha256
5c05352e2d8abf43, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).