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Contents

README

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TLV5632IPWR

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-20

TLV5632IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Digital ground for the digital interface circuitry.
2 DIN input Digital serial data input; the 16-bit word (4 control and 12 data bits) is shifted in MSB first on the falling edges of SCLK after FS goes low.
3 SCLK input Serial clock input, with a maximum serial clock frequency of 30 MHz.
4 FS input Frame sync input; in µC mode FS must stay low until all 16 data bits are transferred and the DAC updates on its rising edge, while in DSP mode FS must stay low for at least 20 ns.
5 PRE input Preset input; when driven low and LDAC is asserted, all DAC outputs go to the value stored in the preset register, and it is asynchronous to the clock.
6 OUTE output DAC E buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
7 OUTF output DAC F buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
8 OUTG output DAC G buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
9 OUTH output DAC H buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
10 AGND power_in Analog ground for the DAC and output circuitry.
11 AVDD power_in Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation; AVDD must power up before DVDD for correct power-on reset.
12 OUTA output DAC A buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
13 OUTB output DAC B buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
14 OUTC output DAC C buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
15 OUTD output DAC D buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load.
16 REF bidirectional Voltage reference input/output; accepts an external reference from 0 V to AVDD, or outputs an internal 1.024 V or 2.048 V reference that needs a 1 µF to 10 µF capacitor in parallel with 100 pF when used.
17 MODE input DSP/µC mode select pin: high selects µC mode, and not connected (NC) selects DSP mode.
18 LDAC input Load DAC; DAC outputs are updated only while LDAC is low, and it is an asynchronous input with a minimum low pulse width of 10 ns.
19 DOUT output Digital serial data output that reproduces the DIN data with a 16-clock-cycle delay when DOUT is enabled, for daisy-chaining.
20 DVDD power_in Digital power supply, using the same 4.5 V to 5.5 V or 2.7 V to 3.3 V ranges as AVDD and powering up after AVDD.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: TLV5632IPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tlv5632ipwr-etched.step / tlv5632ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv5632ipwr.step / tlv5632ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 fca921911e680eae, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF