component
SN74HCT540DWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCT540DWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20
SN74HCT540DWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output enable input 1; outputs disabled to high-impedance when OE1 or OE2 is high |
| 2 | A1 | input | Data input 1 to buffer channel 1; produces inverted output at Y1 |
| 3 | A2 | input | Data input 2 to buffer channel 2; produces inverted output at Y2 |
| 4 | A3 | input | Data input 3 to buffer channel 3; produces inverted output at Y3 |
| 5 | A4 | input | Data input 4 to buffer channel 4; produces inverted output at Y4 |
| 6 | A5 | input | Data input 5 to buffer channel 5; produces inverted output at Y5 |
| 7 | A6 | input | Data input 6 to buffer channel 6; produces inverted output at Y6 |
| 8 | A7 | input | Data input 7 to buffer channel 7; produces inverted output at Y7 |
| 9 | A8 | input | Data input 8 to buffer channel 8; produces inverted output at Y8 |
| 10 | GND | power_in | Ground reference |
| 11 | Y8 | tri_state | Inverted output 8; high-impedance when OE1 or OE2 is high |
| 12 | Y7 | tri_state | Inverted output 7; high-impedance when OE1 or OE2 is high |
| 13 | Y6 | tri_state | Inverted output 6; high-impedance when OE1 or OE2 is high |
| 14 | Y5 | tri_state | Inverted output 5; high-impedance when OE1 or OE2 is high |
| 15 | Y4 | tri_state | Inverted output 4; high-impedance when OE1 or OE2 is high |
| 16 | Y3 | tri_state | Inverted output 3; high-impedance when OE1 or OE2 is high |
| 17 | Y2 | tri_state | Inverted output 2; high-impedance when OE1 or OE2 is high |
| 18 | Y1 | tri_state | Inverted output 1; high-impedance when OE1 or OE2 is high |
| 19 | OE2 | input | Output enable input 2; outputs disabled to high-impedance when OE1 or OE2 is high |
| 20 | VCC | power_in | Positive supply voltage, 4.5 V to 5.5 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HCT540DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hct540dwr-etched.step/sn74hct540dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct540dwr.step/sn74hct540dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
e525a0e95e7bfb12, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).