component
MSP430F4793IPZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F4793IPZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
MSP430F4793IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC1 | power_in | Digital supply voltage, positive terminal. |
| 2 | A0.0+ | input | SD16_A positive analog input A0.0; open connection recommended if the input is unused. |
| 3 | A0.0- | input | SD16_A negative analog input A0.0; open connection recommended if the input is unused. |
| 4 | A1.0+ | input | SD16_A positive analog input A1.0; open connection recommended if the input is unused. |
| 5 | A1.0- | input | SD16_A negative analog input A1.0; open connection recommended if the input is unused. |
| 6 | A2.0+ | input | SD16_A positive analog input A2.0; open connection recommended if the input is unused. |
| 7 | A2.0- | input | SD16_A negative analog input A2.0; open connection recommended if the input is unused. |
| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 9 | XOUT | output | Output terminal of crystal oscillator XT1. |
| 10 | VREF | power_in | Input for an external reference voltage or internal reference voltage output, which can be used as mid-voltage. |
| 11 | NC | unconnected | Internally not connected; can be connected to VSS. |
| 12 | P5.1/S0 | bidirectional | General-purpose digital I/O, or LCD segment output 0. |
| 13 | S1 | output | LCD segment output 1. |
| 14 | P10.7/S2 | bidirectional | General-purpose digital I/O, or LCD segment output 2. |
| 15 | P10.6/S3 | bidirectional | General-purpose digital I/O, or LCD segment output 3. |
| 16 | P10.5/S4 | bidirectional | General-purpose digital I/O, or LCD segment output 4. |
| 17 | P10.4/S5 | bidirectional | General-purpose digital I/O, or LCD segment output 5. |
| 18 | P10.3/S6 | bidirectional | General-purpose digital I/O, or LCD segment output 6. |
| 19 | P10.2/S7 | bidirectional | General-purpose digital I/O, or LCD segment output 7. |
| 20 | P10.1/S8 | bidirectional | General-purpose digital I/O, or LCD segment output 8. |
| 21 | P10.0/S9 | bidirectional | General-purpose digital I/O, or LCD segment output 9. |
| 22 | P9.7/S10 | bidirectional | General-purpose digital I/O, or LCD segment output 10. |
| 23 | P9.6/S11 | bidirectional | General-purpose digital I/O, or LCD segment output 11. |
| 24 | P9.5/S12 | bidirectional | General-purpose digital I/O, or LCD segment output 12. |
| 25 | P9.4/S13 | bidirectional | General-purpose digital I/O, or LCD segment output 13. |
| 26 | P9.3/S14 | bidirectional | General-purpose digital I/O, or LCD segment output 14. |
| 27 | P9.2/S15 | bidirectional | General-purpose digital I/O, or LCD segment output 15. |
| 28 | P9.1/S16 | bidirectional | General-purpose digital I/O, or LCD segment output 16. |
| 29 | P9.0/S17 | bidirectional | General-purpose digital I/O, or LCD segment output 17. |
| 30 | P8.7/S18 | bidirectional | General-purpose digital I/O, or LCD segment output 18. |
| 31 | P8.6/S19 | bidirectional | General-purpose digital I/O, or LCD segment output 19. |
| 32 | P8.5/S20 | bidirectional | General-purpose digital I/O, or LCD segment output 20. |
| 33 | P8.4/S21 | bidirectional | General-purpose digital I/O, or LCD segment output 21. |
| 34 | P8.3/S22 | bidirectional | General-purpose digital I/O, or LCD segment output 22. |
| 35 | P8.2/S23 | bidirectional | General-purpose digital I/O, or LCD segment output 23. |
| 36 | P8.1/S24 | bidirectional | General-purpose digital I/O, or LCD segment output 24. |
| 37 | P8.0/S25 | bidirectional | General-purpose digital I/O, or LCD segment output 25. |
| 38 | P7.7/S26 | bidirectional | General-purpose digital I/O, or LCD segment output 26. |
| 39 | P7.6/S27 | bidirectional | General-purpose digital I/O, or LCD segment output 27. |
| 40 | P7.5/S28 | bidirectional | General-purpose digital I/O, or LCD segment output 28. |
| 41 | P7.4/S29 | bidirectional | General-purpose digital I/O, or LCD segment output 29. |
| 42 | P7.3/S30 | bidirectional | General-purpose digital I/O, or LCD segment output 30. |
| 43 | P7.2/S31 | bidirectional | General-purpose digital I/O, or LCD segment output 31. |
| 44 | P7.1/S32 | bidirectional | General-purpose digital I/O, or LCD segment output 32. |
| 45 | P7.0/S33 | bidirectional | General-purpose digital I/O, or LCD segment output 33. |
| 46 | P4.7/S34 | bidirectional | General-purpose digital I/O, or LCD segment output 34. |
| 47 | P4.6/S35 | bidirectional | General-purpose digital I/O, or LCD segment output 35. |
| 48 | P4.5/UCB1CLK/UCA1STE/S36 | bidirectional | General-purpose digital I/O, USCI_B1 clock input/output, USCI_A1 slave transmit enable, or LCD segment output 36. |
| 49 | P4.4/UCB1SOMI/UCB1SCL/S37 | bidirectional | General-purpose digital I/O, USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode, or LCD segment output 37. |
| 50 | P4.3/UCB1SIMO/UCB1SDA/S38 | bidirectional | General-purpose digital I/O, USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode, or LCD segment output 38. |
| 51 | P4.2/UCB1STE/UCA1CLK/S39 | bidirectional | General-purpose digital I/O, USCI_B1 slave transmit enable, USCI_A1 clock input/output, or LCD segment output 39. |
| 52 | COM0 | output | LCD backplane common output COM0 (COM0 to COM3 are used for LCD backplanes). |
| 53 | P5.2/COM1 | bidirectional | General-purpose digital I/O, or LCD common output COM1 for backplane use. |
| 54 | P5.3/COM2 | bidirectional | General-purpose digital I/O, or LCD common output COM2 for backplane use. |
| 55 | P5.4/COM3 | bidirectional | General-purpose digital I/O, or LCD common output COM3 for backplane use. |
| 56 | P5.5/R03 | bidirectional | General-purpose digital I/O, or input port of the lowest analog LCD level (V5). |
| 57 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O, external reference voltage input for regulated LCD voltage, or input port of the third most positive analog LCD level (V4 or V3). |
| 58 | P5.7/R23 | bidirectional | General-purpose digital I/O, or input port of the second most positive analog LCD level (V2). |
| 59 | LCDCAP/R33 | input | LCD capacitor connection, and input/output port of the most positive analog LCD level (V1); the datasheet classifies this pin as input (I) in its terminal table. |
| 60 | DVCC2 | power_in | Digital supply voltage, positive terminal. |
| 61 | DVSS2 | power_in | Digital supply voltage, negative terminal (ground). |
| 62 | P4.1/UCA1RXD/UCA1SOMI | bidirectional | General-purpose digital I/O, USCI_A1 receive data input in UART mode, or slave out/master in in SPI mode. |
| 63 | P4.0/UCA1TXD/UCA1SIMO | bidirectional | General-purpose digital I/O, USCI_A1 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 64 | P3.7 | bidirectional | General-purpose digital I/O. |
| 65 | P3.6 | bidirectional | General-purpose digital I/O. |
| 66 | P3.5 | bidirectional | General-purpose digital I/O. |
| 67 | P3.4 | bidirectional | General-purpose digital I/O. |
| 68 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, USCI_B0 clock input/output, or USCI_A0 slave transmit enable. |
| 69 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, USCI_B0 slave out/master in in SPI mode, or SCL I2C clock in I2C mode. |
| 70 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, USCI_B0 slave in/master out in SPI mode, or SDA I2C data in I2C mode. |
| 71 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O, USCI_B0 slave transmit enable, or USCI_A0 clock input/output. |
| 72 | P2.7 | bidirectional | General-purpose digital I/O. |
| 73 | P2.6/CAOUT | bidirectional | General-purpose digital I/O, or Comparator_A output. |
| 74 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, USCI_A0 receive data input in UART mode, or slave out/master in in SPI mode. |
| 75 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, USCI_A0 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 76 | P2.3/TB2 | bidirectional | General-purpose digital I/O, or Timer_B3 CCR2 (capture CCI2A/CCI2B input, compare Out2 output). |
| 77 | P2.2/TB1 | bidirectional | General-purpose digital I/O, or Timer_B3 CCR1 (capture CCI1A/CCI1B input, compare Out1 output). |
| 78 | P2.1/TB0 | bidirectional | General-purpose digital I/O, or Timer_B3 CCR0 (capture CCI0A/CCI0B input, compare Out0 output). |
| 79 | P2.0/TA2 | bidirectional | General-purpose digital I/O, or Timer_A capture CCI2A input / compare Out2 output. |
| 80 | P1.7/CA1 | bidirectional | General-purpose digital I/O, or Comparator_A input. |
| 81 | P1.6/CA0 | bidirectional | General-purpose digital I/O, or Comparator_A input. |
| 82 | P1.5/TACLK/ACLK | bidirectional | General-purpose digital I/O, Timer_A TACLK clock input, or ACLK output divided by 1, 2, 4 or 8. |
| 83 | P1.4/TBCLK/SMCLK | bidirectional | General-purpose digital I/O, Timer_B3 TBCLK input clock, or submain system clock SMCLK output. |
| 84 | P1.3/TBOUTH/SVSOUT | bidirectional | General-purpose digital I/O, switch of all Timer_B PWM outputs to high impedance (TBOUTH), or SVS comparator output (SVSOUT). |
| 85 | P1.2/TA1 | bidirectional | General-purpose digital I/O, or Timer_A capture CCI1A input / compare Out1 output. |
| 86 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O, Timer_A capture CCI0B input, MCLK output, or BSL receive; TA0 is only an input on this pin. |
| 87 | P1.0/TA0 | bidirectional | General-purpose digital I/O, Timer_A capture CCI0A input / compare Out0 output, or BSL transmit. |
| 88 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 89 | XT2IN | input | Input port for crystal oscillator XT2; only standard crystals can be connected. |
| 90 | TDO/TDI | bidirectional | Test data output port; carries TDO/TDI data output or programming data input. |
| 91 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to this pin. |
| 92 | TMS | input | Test mode select; used as an input for device programming and test. |
| 93 | TCK | input | Test clock; the clock input port for device programming and test. |
| 94 | RST/NMI | input | Reset input or nonmaskable interrupt input port. |
| 95 | P5.0/SVSIN | bidirectional | General-purpose digital I/O, or analog input to the supply voltage supervisor (SVSIN). |
| 96 | A3.0+ | input | SD16_A positive analog input A3.0 (MSP430x47x4 only); not connected in MSP430x47x3 devices, open connection recommended. |
| 97 | A3.0- | input | SD16_A negative analog input A3.0 (MSP430x47x4 only); not connected in MSP430x47x3 devices, open connection recommended. |
| 98 | AVSS | power_in | Analog supply voltage, negative terminal (ground). |
| 99 | DVSS1 | power_in | Digital supply voltage, negative terminal (ground). |
| 100 | AVCC | power_in | Analog supply voltage, positive terminal; must not power up prior to DVCC1/DVCC2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F4793IPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f4793ipzr-etched.step/msp430f4793ipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f4793ipzr.step/msp430f4793ipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (84 pp, sha256
ddafac1ca61d1dc4, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).