component

USB5744T

Public Made by Adom

by adom

Microchip Tech USB ICs, VQFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232usb5744tfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

USB5744T

Microchip Tech · USB ICs · VQFN-56-EP(7x7)

USB5744T from Microchip Tech, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB2DN_DP1/PRT_DIS_P1 bidirectional USB 2.0 downstream port 1 data plus (D+), also the port 1 D+ disable configuration strap latched at reset (tie to 3.3 V together with PRT_DIS_M1 to disable the port); reset state PD-15k.
2 USB2DN_DM1/PRT_DIS_M1 bidirectional USB 2.0 downstream port 1 data minus (D-), also the port 1 D- disable configuration strap latched at reset; reset state PD-15k.
3 USB3DN_TXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data plus; leave floating if unused.
4 USB3DN_TXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data minus; leave floating if unused.
5 VDD12 power_in +1.2 V core power.
6 USB3DN_RXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data plus; leave floating if unused.
7 USB3DN_RXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data minus; leave floating if unused.
8 USB2DN_DP2/PRT_DIS_P2 bidirectional USB 2.0 downstream port 2 data plus (D+), also the port 2 D+ disable configuration strap; reset state PD-15k.
9 USB2DN_DM2/PRT_DIS_M2 bidirectional USB 2.0 downstream port 2 data minus (D-), also the port 2 D- disable configuration strap; reset state PD-15k.
10 USB3DN_TXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data plus; leave floating if unused.
11 USB3DN_TXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data minus; leave floating if unused.
12 VDD12 power_in +1.2 V core power.
13 USB3DN_RXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data plus; leave floating if unused.
14 USB3DN_RXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data minus; leave floating if unused.
15 VDD12 power_in +1.2 V core power.
16 VDD33 power_in +3.3 V power and internal regulator input.
17 USB2DN_DP3/PRT_DIS_P3 bidirectional USB 2.0 downstream port 3 data plus (D+), also the port 3 D+ disable configuration strap; reset state PD-15k.
18 USB2DN_DM3/PRT_DIS_M3 bidirectional USB 2.0 downstream port 3 data minus (D-), also the port 3 D- disable configuration strap; reset state PD-15k.
19 USB3DN_TXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data plus; leave floating if unused.
20 USB3DN_TXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data minus; leave floating if unused.
21 VDD12 power_in +1.2 V core power.
22 USB3DN_RXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data plus; leave floating if unused.
23 USB3DN_RXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data minus; leave floating if unused.
24 USB2DN_DP4/PRT_DIS_P4 bidirectional USB 2.0 downstream port 4 data plus (D+), also the port 4 D+ disable configuration strap; reset state PD-15k.
25 USB2DN_DM4/PRT_DIS_M4 bidirectional USB 2.0 downstream port 4 data minus (D-), also the port 4 D- disable configuration strap; reset state PD-15k.
26 USB3DN_TXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data plus; leave floating if unused.
27 USB3DN_TXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data minus; leave floating if unused.
28 VDD12 power_in +1.2 V core power.
29 USB3DN_RXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data plus; leave floating if unused.
30 USB3DN_RXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data minus; leave floating if unused.
31 VDD33 power_in +3.3 V power and internal regulator input.
32 PRT_CTL4/GANG_PWR bidirectional Port 4 power enable output / overcurrent sense input (internal pull-up; leave floating if unused); when pulled high enables gang mode and serves as the gang power pin.
33 VDD12 power_in +1.2 V core power.
34 PRT_CTL3 bidirectional Port 3 power enable output (active high) / overcurrent sense input from an external current monitor; leave floating if unused.
35 PRT_CTL2 bidirectional Port 2 power enable output (active high) / overcurrent sense input from an external current monitor; leave floating if unused.
36 PRT_CTL1 bidirectional Port 1 power enable output (active high) / overcurrent sense input from an external current monitor; leave floating if unused.
37 VBUS_DET input Detects upstream bus power; connect to upstream VBUS through a 50 k by 100 k resistor divider to provide 3.3 V (also usable as GPIO16).
38 SPI_CLK/SMCLK bidirectional SPI clock output to the serial ROM in SPI mode, or SMBus clock (open-drain) in SMBus slave mode; also GPIO4; a 10 k pull-up selects SMBus mode.
39 SPI_DO/SMDAT bidirectional SPI data output in SPI mode, or SMBus data in SMBus slave mode; also GPIO5; a 10 k pull-up selects SMBus mode.
40 SPI_DI/CFG_BC_EN bidirectional SPI data input in SPI mode (also GPIO9), or the battery charging configuration strap (CFG_BC_EN) in SMBus mode, set by an external resistor.
41 SPI_CE_N/CFG_NON_REM bidirectional Active-low SPI chip enable output in SPI mode (also GPIO7), or the non-removable port configuration strap (CFG_NON_REM) in SMBus mode.
42 RESET_N input Active-low Schmitt-trigger reset input that puts the device into Reset (Standby) Mode.
43 VDD12 power_in +1.2 V core power.
44 VDD33 power_in +3.3 V power and internal regulator input.
45 USB2UP_DP bidirectional USB 2.0 upstream data plus (D+).
46 USB2UP_DM bidirectional USB 2.0 upstream data minus (D-).
47 USB3UP_TXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data plus.
48 USB3UP_TXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data minus.
49 VDD12 power_in +1.2 V core power.
50 USB3UP_RXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data plus.
51 USB3UP_RXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data minus.
52 ATEST input Analog test pin that must always be connected to ground.
53 XTALO output External 25 MHz crystal output; leave unconnected when driving XTALI/CLK_IN with a single-ended clock.
54 XTALI/CLK_IN input External 25 MHz crystal input or single-ended 25 MHz reference clock input.
55 VDD33 power_in +3.3 V power and internal regulator input.
56 RBIAS passive A 12.0 k (+/-1%) resistor is attached from ground to this pin to set the transceiver's internal bias settings.
57 VSS power_in Exposed pad, common ground; must be connected to the ground plane with a via array.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-56-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
+1.2 V Supply Voltage (abs max) VDD12 -0.5 1.32 V 32
+3.3 V Supply Voltage (abs max) VDD33 -0.5 4.6 V 32
Voltage on input signal pins -0.5 4.6 V with respect to ground 32
Positive voltage on XTALI/CLK_IN 3.63 V with respect to ground 32
Positive voltage on USB DP/DM pins 6 V with respect to ground 32
Positive voltage on USB3UP_xxxx/USB3DN_xxxx pins 1.32 V with respect to ground 32
Storage Temperature -55 150 °C 32
Junction Temperature 125 °C 32
HBM ESD Performance 3 kV 32
+1.2 V Supply Voltage VDD12 1.08 1.32 V 32
+3.3 V Supply Voltage VDD33 3 3.6 V 32
Input Signal Pins Voltage -0.3 3.6 V 32
XTALI/CLK_IN Voltage -0.3 3.6 V 32
USB 2.0 DP/DM Signal Pins Voltage -0.3 5.5 V 32
USB 3.2 Gen 1 USB3UP_xxxx/USB3DN_xxxx Pins Voltage -0.3 1.32 V 32
Ambient Operating Temperature, commercial TA 0 70 °C commercial version, still air 32
Ambient Operating Temperature, industrial TA -40 85 °C industrial version, still air 32
+1.2 V Supply Voltage Rise Time TRT 5 ms Figure 10-1 32
+3.3 V Supply Voltage Rise Time TRT 5 ms Figure 10-1 32
O6 Low Output Level VOL 0.4 V IOL = 6 mA 35
O12 Low Output Level VOL 0.4 V IOL = 12 mA 35
OD12 Low Output Level VOL 0.4 V IOL = 12 mA 35
IS Schmitt Trigger Hysteresis VHYS 9 20 40 mV VIHT - VILT 35
Configuration strap hold after power supplies at operational levels tcsh 1 ms 36
RESET_N input assertion time trstia 5 µs 37
Configuration strap pins hold after RESET_N deassertion tcsh 1 ms 37
SPI clock frequency (30 MHz operation) tfc 30 MHz 38
SPI clock frequency (60 MHz operation) tfc 60 MHz 38
Crystal Frequency Tolerance Ftol -50 50 PPM @ 25°C 39
Crystal Frequency Stability Over Temp Ftemp -50 50 PPM 39
Crystal Total Allowable PPM Budget -100 100 PPM 39
Crystal Drive Level PW 100 uW 39
Crystal Equivalent Series Resistance R1 50 Ω 39
Crystal Frequency Ffund 25 MHz 39
Crystal Load Capacitance CL 20 pF 39
Crystal Shunt Capacitance CO 7 pF 39
Junction-to-ambient thermal resistance θJA 30 °C/W velocity 0 m/s 33
Junction-to-ambient thermal resistance θJA 26 °C/W velocity 1 m/s 33
Junction-to-top thermal characterization ψJT 0.2 °C/W velocity 0 m/s 33
Junction-to-top thermal characterization ψJT 0.3 °C/W velocity 1 m/s 33
Junction-to-case thermal resistance θJC 2.6 °C/W velocity 0 m/s 33
Maximum Power Dissipation PD(max) 1400 mW 33

CAD (KiCad official)

  • Symbol: USB5744T
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: usb5744t-etched.step / usb5744t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb5744t.step / usb5744t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (51 pp, sha256 b000b915ca780ce6, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF