component
FD2109S
Public Made by Adomby adom
Fortior Tech Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFD2109S
Fortior Tech · Gate Drivers · SOIC-8
FD2109S from Fortior Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side supply voltage, recommended 10 V to 18 V referenced to COM, with absolute maximum -0.3 V to 24 V. |
| 2 | VB | power_in | High-side floating supply, recommended VS+10 V to VS+18 V, with absolute maximum of 204 V referenced to COM. |
| 3 | HO | output | High-side gate drive output, swinging between VS and VB (absolute range VS-0.3 V to VB+0.3 V), in phase with HIN. |
| 4 | VS | power_in | High-side floating offset voltage, allowed from VB-24 V to VB+0.3 V, with dVS/dt limited to 50 V/ns. |
| 5 | LIN | input | Low-side logic input, compatible with 3.3 V and 5 V logic (VIL max 0.8 V, VIH min 2.7 V), with absolute range -0.3 V to VCC+0.3 V. |
| 6 | HIN | input | High-side logic input, compatible with 3.3 V and 5 V logic (VIL max 0.8 V, VIH min 2.7 V), with absolute range -0.3 V to VCC+0.3 V. |
| 7 | COM | power_in | Ground reference for all pins; all voltages in the datasheet are referenced to COM. |
| 8 | LO | output | Low-side gate drive output, swinging between COM and VCC (absolute range -0.3 V to VCC+0.3 V), in phase with LIN. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fortior Tech |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 高侧浮动绝对电压 (VB absolute max) | VB | -0.3 | 204 | V | 2 | ||
| 低侧供电电压 (VCC absolute max) | VCC | -0.3 | 24 | V | 2 | ||
| 低侧输出电压 (VLO absolute max) | VLO | -0.3 | V | 2 | |||
| 逻辑输入电压 (HIN, LIN) absolute max | VIN | -0.3 | V | 2 | |||
| 偏移电压压摆率范围 (dVS/dt) | dVS/dt | 50 | V/ns | 2 | |||
| 功率耗散 (PD) | PD | 0.625 | W | TA≤25C, SOIC-8 | 2 | ||
| 结对环境的热阻 (RthJA) | RthJA | 200 | C/W | SOIC-8 | 2 | ||
| 结温范围 (Tj) | Tj | 150 | C | 2 | |||
| 储存温度范围 (Tstg) | Tstg | -55 | 150 | C | 2 | ||
| 低侧供电电压 (VCC recommended) | VCC | 10 | 18 | V | 2 | ||
| 低侧输出电压 (VLO recommended) | VLO | 0 | V | 2 | |||
| 逻辑输入电压 (HIN, LIN) recommended | VIN | 0 | V | 2 | |||
| 环境温度 (TA) | TA | -40 | 125 | C | 2 | ||
| 高电平输入阈值电压 (VIH) | VIH | 2.7 | V | 3 | |||
| 低电平输入阈值电压 (VIL) | VIL | 0.8 | V | 3 | |||
| VCC欠压保护开启电压 (VCCUV+) | VCCUV+ | 7.9 | 8.8 | 9.7 | V | 3 | |
| VCC欠压保护关断电压 (VCCUV-) | VCCUV- | 7.3 | 8.2 | 9.1 | V | 3 | |
| VCC欠压保护迟滞电压 (VCCUVH) | VCCUVH | 0.4 | 0.6 | V | 3 | ||
| VBS 欠压保护开启电压 (VBSUV+) | VBSUV+ | 7.9 | 8.8 | 9.7 | V | 3 | |
| VBS 欠压保护关断电压 (VBSUV-) | VBSUV- | 7.3 | 8.2 | 9.1 | V | 3 | |
| VBS 欠压保护迟滞电压 (VBSUVH) | VBSUVH | 0.4 | 0.6 | V | 3 | ||
| 悬浮电源漏电流 (ILK) | ILK | 0.1 | 5 | μA | VB=VS=180V | 3 | |
| VBS 静态电流 (IQBS) | IQBS | 100 | 200 | μA | VIN=0V 或 5V | 3 | |
| VCC静态电流 (IQCC) | IQCC | 300 | 600 | uA | VIN =0V 或 5V | 3 | |
| LIN 高电平输入偏置电流 (ILIN+) | ILIN+ | 30 | 50 | μA | VLIN=5V | 3 | |
| LIN 低电平输入偏置电流 (ILIN-) | ILIN- | 1 | μA | VLIN=0V | 3 | ||
| HIN 高电平输入偏置电流 (IHIN+) | IHIN+ | 30 | 50 | μA | VHIN=5V | 3 | |
| HIN 低电平输入偏置电流 (IHIN-) | IHIN- | 1 | μA | VHIN=0V | 3 | ||
| 高电平输出电压 (VOH) | VOH | 0.12 | 0.2 | V | IO=100mA | 3 | |
| 低电平输出电压 (VOL) | VOL | 0.065 | 0.12 | V | IO=100mA | 3 | |
| 高电平输出短路脉冲电流 (IOH) | IOH | 3 | 5 | A | VO=0V，PWD≤10μs | 3 | |
| 低电平输出短路脉冲电流 (IOL) | IOL | 3 | 5 | A | VO=15V，PWD≤10μs | 3 | |
| 输出上升沿传输时间 (ton) | ton | 380 | 600 | ns | CL=1000pF | 3 | |
| 输出下降沿传输时间 (toff) | toff | 100 | 200 | ns | CL=1000pF | 3 | |
| 输出上升时间 (tr) | tr | 10 | ns | CL=1000pF | 3 | ||
| 输出下降时间 (tf) | tf | 10 | ns | CL=1000pF | 3 | ||
| 死区时间 (DT) | DT | 280 | 500 | ns | 3 | ||
| 高低侧延时匹配 (MT) | MT | 50 | ns | 3 |
CAD (KiCad official)
- Symbol:
FD2109S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
fd2109s-etched.step/fd2109s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fd2109s.step/fd2109s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Fortior Tech datasheet (9 pp, sha256
0ae423a18266cf4f, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).