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TLV320ADC3101IRGER
Public Made by Adomby adom
Texas Instruments ADCs/DACs - Special Purpose, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV320ADC3101IRGER
Texas Instruments · ADCs/DACs - Special Purpose · VQFN-24-EP(4x4)
TLV320ADC3101IRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BCLK | bidirectional | Audio serial data bus bit clock input/output, configurable as input in slave mode or output in master mode |
| 2 | WCLK | bidirectional | Audio serial data bus word clock input/output, configurable as input in slave mode or output in master mode |
| 3 | DOUT | output | Audio serial data output supporting I2S/DSP/LJF/RJF/TDM modes with 16/20/24/32-bit word length and programmable tri-state capability |
| 4 | RESET | input | Active-low asynchronous reset input requiring minimum 10 ns pulse width after power supply stabilization |
| 5 | MICBIAS1 | output | Programmable microphone bias voltage output selectable to 2.0 V, 2.5 V, or AVDD with 4 mA maximum source current |
| 6 | IN3L(M) | input | Analog audio input for left ADC channel, configurable as single-ended or differential minus paired with IN2L(P) |
| 7 | IN2L(P) | input | Analog audio input for left ADC channel, configurable as single-ended or differential plus paired with IN3L(M) |
| 8 | IN1L(P) | input | Analog audio input configurable for left-channel single-ended or differential plus with IN1R(M), with input impedance 35 kΩ to 46.3 kΩ depending on configuration |
| 9 | AVSS | power_in | Analog ground supply reference, 0 V nominal |
| 10 | AVDD | power_in | Analog power supply input, 2.6 V to 3.6 V operating range with 0.1 µF and 1 µF decoupling capacitors recommended |
| 11 | IN1R(M) | input | Analog audio input configurable for left-channel single-ended or differential minus with IN1L(P), or right-channel operation |
| 12 | IN2R(P) | input | Analog audio input for right ADC channel, configurable as single-ended or differential plus paired with IN3R(M) |
| 13 | IN3R(M) | input | Analog audio input for right ADC channel, configurable as single-ended or differential minus paired with IN2R(P) |
| 14 | MICBIAS2 | output | Programmable microphone bias voltage output selectable to 2.0 V, 2.5 V, or AVDD with 4 mA maximum source current |
| 15 | I2C_ADR0 | input | I2C slave address configuration pin defining bit 0 of 7-bit address, tied high or low at board design time |
| 16 | I2C_ADR1 | input | I2C slave address configuration pin defining bit 1 of 7-bit address, tied high or low at board design time |
| 17 | SCL | bidirectional | I2C serial clock open-drain input/output supporting standard mode (100 kHz) and fast mode (400 kHz) with external pull-up resistor required |
| 18 | SDA | bidirectional | I2C serial data open-drain input/output supporting standard mode (100 kHz) and fast mode (400 kHz) with external pull-up resistor required |
| 19 | DMDIN/GPIO1 | bidirectional | Digital microphone data input or programmable general-purpose input/output with multifunction capability for secondary audio interface or clock distribution |
| 20 | DMCLK/GPIO2 | bidirectional | Digital microphone clock or programmable general-purpose input/output with multifunction capability for secondary audio interface or PLL clock input |
| 21 | IOVDD | power_in | Digital I/O power supply input, 1.1 V to 3.6 V operating range with 0.1 µF decoupling capacitor recommended |
| 22 | DVDD | power_in | Digital core power supply input, 1.65 V to 1.95 V operating range with 0.1 µF and 1 µF decoupling capacitors recommended |
| 23 | DVSS | power_in | Digital ground supply reference, 0 V nominal, connected to thermal pad |
| 24 | MCLK | input | Master clock input for ADC and internal clock generation, 512 kHz to 50 MHz operating range supporting fixed clock divider or PLL multiplication |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Data Acquisition |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
TLV320ADC3101IRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tlv320adc3101irger-etched.step/tlv320adc3101irger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv320adc3101irger.step/tlv320adc3101irger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (96 pp, sha256
0ffb85b5833b851e, retrieved 2026-09-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).