component
LM25117QPMHX
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM25117QPMHX
Texas Instruments · DC-DC Converters · HTSSOP-20
LM25117QPMHX from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UVLO | input | Undervoltage lockout programming pin: below 0.4V the regulator is shut down, 0.4V to 1.25V is standby, above 1.25V enables switching, with a 20 µA hysteresis sink when above 1.25V; it must not float. |
| 2 | DEMB | input | Optional logic input that enables diode emulation when low (internal 50 kΩ pull-down, so floating also enables it), and must be above 3V to keep continuous conduction. |
| 3 | RES | passive | Restart timer pin: a capacitor to AGND sets the hiccup-mode off time, with a 10 µA charge to the 1.25V threshold; tying it to VCC or a voltage above the initial threshold disables the restart timer, and tying it to GND gives latch-off after 256 cycles of current limit. |
| 4 | SS | passive | Soft-start pin: an external capacitor and the internal 10 µA sink set the soft-start ramp, and the pin is held low when VCC is below 4V, UVLO is below 1.25V, or during thermal shutdown. |
| 5 | RT | passive | Oscillator timing pin: a resistor to AGND sets the switching frequency (recommended maximum 750 kHz), the nominal RT voltage is 1.25V, and an AC-coupled positive pulse above the 2.6V to 3.95V sync threshold synchronizes the oscillator. |
| 6 | AGND | power_in | Analog ground for the internal 0.8V reference and analog circuitry, and the return for the RT, UVLO, and other low-power ground connections. |
| 7 | VCCDIS | input | Disables the internal VCC regulator when pulled above the 1.25V threshold (1.22V to 1.29V), and has an internal 500 kΩ pull-down so the regulator stays enabled when the pin floats. |
| 8 | FB | input | Feedback input to the inverting input of the internal error amplifier, which regulates to the 0.8V reference (788 mV to 812 mV) through the output divider. |
| 9 | COMP | output | Error amplifier output, where the loop compensation network is connected between COMP and FB. |
| 10 | CM | output | Current monitor output providing the average sensed inductor current, connected between CM and AGND; leave floating if unused. |
| 11 | RAMP | passive | PWM ramp pin: an RC network between SW, RAMP and AGND sets the simulated inductor-current ramp slope, the ramp capacitor must be discharged within the minimum off-time and kept below 2 nF, and RRAMP must not connect directly to VIN. |
| 12 | CS | input | Current-sense amplifier input, connected to the high side of the current-sense resistor (sense gain of 10 V/V). |
| 13 | CSG | input | Kelvin ground connection to the low side of the current-sense resistor, used as the reference for the current sense amplifier. |
| 14 | PGND | power_in | Power ground return for the low-side NMOS gate driver, connected directly to the low side of the current-sense resistor. |
| 15 | LO | output | Low-side NMOS gate drive output, routed through a short low-inductance path to the low-side MOSFET gate. |
| 16 | VCC | power_out | Bias supply pin regulated to 7.6V typical (6.85V to 8.2V, no load), decoupled to PGND with low-ESR/ESL capacitance of 0.47 µF to 10 µF placed close to the controller. |
| 17 | SW | passive | Switching node at the high-side NMOS source and low-side NMOS drain, with an absolute maximum range of -3.0V to 45V to AGND. |
| 18 | HO | output | High-side NMOS gate drive output, routed through a short low-inductance path to the high-side MOSFET gate. |
| 19 | HB | power_in | High-side driver bootstrap supply, connected to the external bootstrap diode cathode and bootstrap capacitor, with HB to SW operating range of 4.5V to 14V (absolute maximum 15V). |
| 20 | VIN | power_in | Input supply to the internal VCC regulator, with operating range 4.5V to 42V and absolute maximum of 45V to AGND. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
LM25117QPMHX - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lm25117qpmhx-etched.step/lm25117qpmhx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm25117qpmhx.step/lm25117qpmhx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
ebaf723e350b87ed, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).