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TF23892M-TLH

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by adom

TFSS Gate Drivers, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TF23892M-TLH

TFSS · Gate Drivers · SOIC-28

TF23892M-TLH from TFSS, in a SOIC-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side and logic fixed supply, recommended 10V to 20V with absolute maximum -0.3V to +24V.
2 HIN1* input Logic input for the high-side gate driver output HO1, out of phase with HO1; logic input range VSS to 5V.
3 HIN2* input Logic input for the high-side gate driver output HO2, out of phase with HO2; logic input range VSS to 5V.
4 HIN3* input Logic input for the high-side gate driver output HO3, out of phase with HO3; logic input range VSS to 5V.
5 LIN1* input Logic input for the low-side gate driver output LO1, out of phase with LO1; logic input range VSS to 5V.
6 LIN2* input Logic input for the low-side gate driver output LO2, out of phase with LO2; logic input range VSS to 5V.
7 LIN3* input Logic input for the low-side gate driver output LO3, out of phase with LO3; logic input range VSS to 5V.
8 FO* output Fault output with open drain, signalling over-current and VCC UVLO faults; VFO range VSS to VCC.
9 CS input Analog input for over-current shutdown; over-current detect threshold is typically 500 mV (400 to 600 mV).
10 EN input Logic input for enable functionality; I/O logic functions operate when EN is high, and the outputs shut down when EN is low.
11 RCIN passive External RC network input that defines the FAULT CLEAR delay; internal current source typically 8 uA with a positive threshold of 8.0 V.
12 VSS power_in Logic ground; recommended range -5 to 5 (unit printed as 'C', presumably V).
13 COM power_in Low-side driver return, the reference for the LO outputs and the output VO/IO parameters.
14 LO3 output Low-side gate driver output for phase 3, referenced to COM with VLO range COM to VCC.
15 LO2 output Low-side gate driver output for phase 2, referenced to COM with VLO range COM to VCC.
16 LO1 output Low-side gate driver output for phase 1, referenced to COM with VLO range COM to VCC.
17 NC unconnected No connect.
18 VS3 power_in High-side floating supply return for phase 3; VS offset range up to 600V.
19 HO3 output High-side gate driver output for phase 3, referenced to VS3 with VHO range VS to VB.
20 VB3 power_in High-side floating supply for phase 3; VB recommended at VS+10V to VS+20V.
21 NC unconnected No connect.
22 VS2 power_in High-side floating supply return for phase 2; VS offset range up to 600V.
23 HO2 output High-side gate driver output for phase 2, referenced to VS2 with VHO range VS to VB.
24 VB2 power_in High-side floating supply for phase 2; VB recommended at VS+10V to VS+20V.
25 NC unconnected No connect.
26 VS1 power_in High-side floating supply return for phase 1; VS offset range up to 600V.
27 HO1 output High-side gate driver output for phase 1, referenced to VS1 with VHO range VS to VB.
28 VB1 power_in High-side floating supply for phase 1; VB recommended at VS+10V to VS+20V.

Key specifications

Parameter Value
Manufacturer TFSS
Package SOIC-28
Category Motor Driver ICs
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low side fixed supply voltage VCC 10 20 V 5
Ambient temperature TA -40 125 °C 5
High side floating supply offset voltage VS 600 V Logic operational for VS of -5V to +600V (NOTE3) 5
Logic input voltage (HIN*, LIN*, CS, EN) VIN 5 V 5
Logic Ground VSS -5 5 C 5
High-side floating supply voltage VB -0.3 624 V 5
Low-side output voltage VLO -0.3 V 5
Offset supply transient dVS/dt 50 V/ns 5
Low-side fixed supply voltage VCC -0.3 24 V 5
Logic input voltage (HIN*, LIN*, CS, EN and FO*) VIN -0.3 5.5 V 5
Junction operating temperature TJ 150 °C 5
Lead temperature TL 300 °C soldering, 10 seconds 5
Storage temperature Tstg -55 150 °C 5
Logic input voltage (high threshold, printed as Logic 0 input voltage) VIH 2.4 V NOTE5 6
Logic input voltage (low threshold, printed as Logic 1 input voltage) VIL 0.8 V 6
High level output voltage, VBIAS - VO VOH 0.1 V IO = 0mA 6
Low level output voltage, VO VOL 0.1 V IO = 0mA 6
Offset supply leakage current ILK 10 mA VB = VS = 600V 6
Quiescent VBS supply current IBSQ 10 85 130 µA VIN = 0V or 5V, EN=0V 6
Quiescent VCC supply current ICCQ 1.1 1.6 mA VIN = 0V or 5V, EN=0V 6
Logic input bias current (HO=LO=HIGH) IIN+ 130 200 mA VIN = 0V 6
Logic input bias current (HO=LO=LOW) IIN- 3 20 mA VIN = 5V 6
Logic Enable 1 input bias current IEN+ 50 80 mA VEN = 5V 6
Logic Enable 0 input bias current IEN- 2 mA VEN = 0V 6
VBS and VCC supply under-voltage positive going threshold VBSUV+/VCCUV+ 7.6 8.9 9.9 V 6
VBS and VCC supply under-voltage negative going threshold VBSUV-/VCCUV- 7.1 8.3 9.4 V 6
Output high short circuit pulsed current IO+ 250 350 mA VO = 0V, PW ≤ 10 ms 6
Output low short circuit pulsed current IO- 500 650 mA VO = 15V, PW ≤ 10 ms 6
Overcurrent detect positive threshold VITH+ 400 500 600 mV 6
Overcurrent detect negative threshold VITH- 340 420 500 mV 6
Short-circuit input current ICSIN 5 15 20 µA VCSIN=1V 6
RCIN internal current source IRCIN 6 8 10 µA 6
RCIN positive going threshold voltage VRCINTH+ 8 V 6
RCIN negative going threshold voltage VRCINTH- 5 V Guaranteed by design (NOTE6) 6
Fault output low level voltage VFOL 0.2 0.5 V VCS=1V, IFO=1.5mA 6
RCIN on resistance RDSRCIN 40 75 110 Ω IRCIN=1.5mA 6
Fault output on resistance RDSFO 80 130 180 Ω IFO=1.5mA 6
Turn-on propagation delay tON 200 270 460 ns VS = 0V 7
Turn-off propagation delay tOFF 200 270 460 ns VS = 0V 7
Turn-on rise time tr 40 150 ns VS = 0V 7
Turn-off fall time tf 25 60 ns 7
Delay matching tDM 50 ns 7
Enable low to output shutdown delay tEN 225 260 425 ns 7
CS Pin leading-edge blanking time tBLT 200 300 400 ns 7
Time from CS triggering to FO* turn off tFLT 360 550 760 ns From VCS= 1V to FO* turn off 7
Time from CS triggering to all gate outputs turn off tITRIP 420 615 820 ns From VCS= 1V to starting gate turn off 7
Input filtering time (HIN*, LIN*, EN) tFLTIN 250 ns 7
Fault clear time tFLTCLR 3.1 ms CRCIN = 2nF 7
Deadtime tDT 200 290 420 ns 7
Deadtime matching tDTM 50 ns 7
Output pulse width matching tPM 50 75 ns PWIN >1ms 7

CAD (KiCad official)

  • Symbol: TF23892M-TLH
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28 (KiCad packages3D, STEP)
  • 3D model files: tf23892m-tlh-etched.step / tf23892m-tlh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tf23892m-tlh.step / tf23892m-tlh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TFSS datasheet (10 pp, sha256 40f52201254f2e08, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF