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Contents

README

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TPS2480PWR

Texas Instruments · Surge Protection Devices (SPDs) · TSSOP-20

TPS2480PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDA bidirectional I2C data line; the datasheet gives the absolute maximum voltage as GND - 0.3 V to +6.0 V.
2 SCL input I2C clock input; the datasheet gives the absolute maximum voltage as GND - 0.3 V to VS + 0.3 V.
3 NC unconnected No connection; tie to GND or leave floating.
4 VS power_in Power input for the logic and I2C interface, typically 3 V to 5 V (recommended operating range 3 V to 5.5 V).
5 NC unconnected No connection; tie to GND or leave floating.
6 EN input Device enable input; the GATE driver is enabled only when the positive threshold is exceeded and the internal POR and UVLO thresholds are satisfied, and the pin can also serve as an analog voltage monitor input.
7 VREF power_out Provides a 4.0 V reference for the PROG resistor divider; it is not a supply for other circuitry, so no more than 1 mA may be drawn and up to 1000 pF may be added.
8 PROG input Power-limit setting input that accepts 0.4 V to 4.0 V; voltages greater than 4 V must not be applied.
9 TIMER passive Fault timing capacitor pin; the TIMER pin reaching 4 V latches the TPS2480 off, and it should be tied to ground if the timer feature is not used.
10 GND power_in System ground.
11 PG output Open-drain power good output with an absolute maximum voltage of -0.3 V to 100 V and a sink current limit of 10 mA; it goes high after VDS of the external FET falls to about 1.25 V and a 9 ms deglitch period elapses.
12 OUT input Output voltage feedback input used to measure the external FET VDS as V(SENSE-OUT); its absolute maximum range is -0.3 V to 100 V.
13 GATE output High-side gate drive output for the external N-channel FET, with a 22 mA pull-up from the charge pump and at least 75 mA pull-down; its absolute maximum voltage is -0.3 V to 100 V.
14 SENSE input Current-limit sense input at the external FET drain; it is internally clamped to VCC and its absolute maximum range is -0.3 V to 100 V.
15 VCC power_in Main supply input for the device and FET, with recommended range 9 V to 80 V; the voltage must exceed the POR (about 6 V) and UVLO (about 8 V) thresholds before GATE operation begins.
16 GND power_in System ground.
17 VINP input Kelvin-connected positive (source) side of the current-sense resistor, with input voltage range 0 V to 24 V and typically about 20 mA of sink current.
18 VINM input Kelvin-connected negative (load) side of the current-sense resistor; bus voltage is measured from this pin to GND, with input voltage range 0 V to 24 V.
19 A1 input I2C address-select pin, tied to GND, SDA, SCL, or VS to set one of 16 addresses per the datasheet address table.
20 A0 input I2C address-select pin, tied to GND, SDA, SCL, or VS to set one of 16 addresses per the datasheet address table.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Circuit Protection
Pins 20

CAD (KiCad official)

  • Symbol: TPS2480PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tps2480pwr-etched.step / tps2480pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2480pwr.step / tps2480pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 b6a2a9a5f88be0ad, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF