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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ESP32-S2FR-01

Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad

ESP32-S2FR-01 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDA	power_in	Analog power domain supply input.
2	LNA_IN	bidirectional	RF low-noise amplifier input/output signal for the 2.4 GHz radio.
3	VDD3P3	power_in	Analog power domain supply input.
4	VDD3P3	power_in	Analog power domain supply input.
5	GPIO0	bidirectional	Strapping pin for chip boot mode control with weak pull-up at reset; also RTC_GPIO0 and sar_i2c_scl_0.
6	GPIO1	bidirectional	General-purpose IO also providing TOUCH1, ADC1_CH0 and RTC_GPIO1 functions.
7	GPIO2	bidirectional	General-purpose IO also providing TOUCH2, ADC1_CH1 and RTC_GPIO2 functions; input enabled at reset.
8	GPIO3	bidirectional	General-purpose IO also providing TOUCH3, ADC1_CH2 and RTC_GPIO3 functions.
9	GPIO4	bidirectional	General-purpose IO also providing TOUCH4, ADC1_CH3 and RTC_GPIO4 functions.
10	GPIO5	bidirectional	General-purpose IO also providing TOUCH5, ADC1_CH4 and RTC_GPIO5 functions.
11	GPIO6	bidirectional	General-purpose IO also providing TOUCH6, ADC1_CH5 and RTC_GPIO6 functions.
12	GPIO7	bidirectional	General-purpose IO also providing TOUCH7, ADC1_CH6 and RTC_GPIO7 functions.
13	GPIO8	bidirectional	General-purpose IO also providing TOUCH8, ADC1_CH7 and RTC_GPIO8 functions; SUBSPICS1 alternate function.
14	GPIO9	bidirectional	General-purpose IO also providing TOUCH9, ADC1_CH8 and RTC_GPIO9 functions; input enabled at reset.
15	GPIO10	bidirectional	General-purpose IO also providing TOUCH10, ADC1_CH9 and RTC_GPIO10 functions; input enabled at reset.
16	GPIO11	bidirectional	General-purpose IO also providing TOUCH11, ADC2_CH0 and RTC_GPIO11 functions; input enabled at reset.
17	GPIO12	bidirectional	General-purpose IO also providing TOUCH12, ADC2_CH1 and RTC_GPIO12 functions; input enabled at reset.
18	GPIO13	bidirectional	General-purpose IO also providing TOUCH13, ADC2_CH2 and RTC_GPIO13 functions; input enabled at reset.
19	GPIO14	bidirectional	General-purpose IO also providing TOUCH14, ADC2_CH3 and RTC_GPIO14 functions; input enabled at reset.
20	VDD3P3_RTC	power_in	RTC domain supply input.
21	XTAL_32K_P	bidirectional	Positive 32 kHz clock signal for the crystal or oscillator; also RTC_GPIO15 and ADC2_CH4.
22	XTAL_32K_N	bidirectional	Negative 32 kHz clock signal for the external crystal or oscillator; also RTC_GPIO16 and ADC2_CH5.
23	DAC_1	bidirectional	8-bit DAC channel 1 analog voltage output; also RTC_GPIO17 and ADC2_CH6.
24	DAC_2	bidirectional	8-bit DAC channel 2 analog voltage output; also RTC_GPIO18 and ADC2_CH7.
25	GPIO19	bidirectional	General-purpose IO; default USB_D- function connects to the USB OTG interface; also RTC_GPIO19 and ADC2_CH8.
26	GPIO20	bidirectional	General-purpose IO; default USB_D+ function connects to the USB OTG interface; also RTC_GPIO20 and ADC2_CH9.
27	VDD3P3_RTC_IO	power_in	Supply input for the RTC and part of the digital power domains, powering RTC IO pins.
28	GPIO21	bidirectional	General-purpose IO also providing RTC_GPIO21 function.
29	SPICS1	bidirectional	SPI chip select 1 for in-package PSRAM, powered by VDD_SPI; pin is reserved and should not be used for other purposes.
30	VDD_SPI	power_in	Backup power line input or output for in-package and off-package flash/PSRAM SPI IO, configurable via VDD_SPI voltage control.
31	SPIHD	bidirectional	SPI hold signal (HOLD# or SIO3) for in-package flash/PSRAM, powered by VDD_SPI; reserved for memory use.
32	SPIWP	bidirectional	SPI write-protect signal (WP# or SIO2) for in-package flash/PSRAM, powered by VDD_SPI; reserved for memory use.
33	SPICS0	bidirectional	SPI chip select 0 for in-package flash, powered by VDD_SPI; reserved for memory use.
34	SPICLK	bidirectional	SPI clock for in-package flash/PSRAM, powered by VDD_SPI; reserved for memory use.
35	SPIQ	bidirectional	SPI data line (DO or SO/SIO1) for in-package flash/PSRAM, powered by VDD_SPI; reserved for memory use.
36	SPID	bidirectional	SPI data line (DI or SI/SIO0) for in-package flash/PSRAM, powered by VDD_SPI; reserved for memory use.
37	GPIO33	bidirectional	Powered by VDD_SPI or VDD3P3_CPU; serves as SPI data line IO4 in 8-line SPI mode and can be a GPIO if no 8-line flash/PSRAM is connected.
38	GPIO34	bidirectional	Powered by VDD_SPI or VDD3P3_CPU; serves as SPI data line IO5 in 8-line SPI mode and can be a GPIO if no 8-line flash/PSRAM is connected.
39	GPIO35	bidirectional	Powered by VDD_SPI or VDD3P3_CPU; serves as SPI data line IO6 in 8-line SPI mode and can be a GPIO if no 8-line flash/PSRAM is connected.
40	GPIO36	bidirectional	Powered by VDD_SPI or VDD3P3_CPU; serves as SPI data line IO7 in 8-line SPI mode and can be a GPIO if no 8-line flash/PSRAM is connected.
41	GPIO37	bidirectional	Powered by VDD_SPI or VDD3P3_CPU; serves as SPI DQS signal in 8-line SPI mode and can be a GPIO if no 8-line flash/PSRAM is connected.
42	GPIO38	bidirectional	Powered by VDD3P3_CPU; general-purpose IO also providing FSPIWP and SUBSPIWP functions.
43	MTCK	bidirectional	JTAG test clock input, also GPIO39; input enabled.
44	MTDO	bidirectional	JTAG test data output, also GPIO40.
45	VDD3P3_CPU	power_in	Digital power domain supply input for digital IO pins.
46	MTDI	bidirectional	JTAG test data input, also GPIO41; input enabled.
47	MTMS	bidirectional	JTAG test mode select input, also GPIO42; input enabled.
48	U0TXD	bidirectional	UART0 transmit data, default function with weak pull-up enabled at reset; also GPIO43.
49	U0RXD	bidirectional	UART0 receive data, default function with weak pull-up enabled at reset; also GPIO44.
50	GPIO45	bidirectional	Strapping pin controlling VDD_SPI voltage, with weak pull-down enabled at reset.
51	VDDA	power_in	Analog power domain supply input.
52	XTAL_N	passive	Negative differential external clock input/output connected to the chip oscillator.
53	XTAL_P	passive	Positive differential external clock input/output connected to the chip oscillator.
54	VDDA	power_in	Analog power domain supply input.
55	GPIO46	input	Input-only GPIO with fixed pull-down; strapping pin for chip boot mode and ROM message printing control.
56	CHIP_PU	input	Chip enable pin: high starts the chip, low shuts it down; must not be left floating.
57	GND	power_in	External ground connection, serving as the ground return for the package.

Key specifications

Parameter	Value
Manufacturer	Espressif Systems
Package	56-VFQFN Exposed Pad
Category	RF and Wireless
Pins	57

CAD (KiCad official)

Symbol: ESP32-S2FR-01
Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm
3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
3D model files: esp32-s2fr-01-etched.step / esp32-s2fr-01-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-s2fr-01.step / esp32-s2fr-01.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Espressif Systems datasheet (65 pp, sha256 7c0c54f11e79cc77, retrieved 2026-10-27, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF