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CY8C4025AZI-S413

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Cypress Semicon CYPRESS, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c4025azi-s413factory-2.0.0extractor-text
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Symbol & Footprint

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Contents

README

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CY8C4025AZI-S413

Cypress Semicon · CYPRESS · TQFP-48(7x7)

CY8C4025AZI-S413 from Cypress Semicon, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional GPIO port 1 bit 7 (analog, digital or CAPSENSE capable) with no alternate peripheral function listed.
2 P2.0 bidirectional GPIO port 2 bit 0 with Smart I/O prgio[0].io[0], tcpwm.line[4]:0, csd.comp, SCB1 I2C SCL and SPI MOSI alternate functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with Smart I/O prgio[0].io[1], tcpwm.line_compl[4]:0, SCB1 I2C SDA and SPI MISO alternate functions.
4 P2.2 bidirectional GPIO port 2 bit 2 with Smart I/O prgio[0].io[2] and SCB1 SPI clock alternate function.
5 P2.3 bidirectional GPIO port 2 bit 3 with Smart I/O prgio[0].io[3] and SCB1 SPI select0 alternate function.
6 P2.4 bidirectional GPIO port 2 bit 4 with Smart I/O prgio[0].io[4], tcpwm.line[0]:1 and SCB1 SPI select1 alternate functions.
7 P2.5 bidirectional GPIO port 2 bit 5 with Smart I/O prgio[0].io[5], tcpwm.line_compl[0]:1 and SCB1 SPI select2 alternate functions.
8 P2.6 bidirectional GPIO port 2 bit 6 with Smart I/O prgio[0].io[6], tcpwm.line[1]:1 and SCB1 SPI select3 alternate functions.
9 P2.7 bidirectional GPIO port 2 bit 7 with Smart I/O prgio[0].io[7], tcpwm.line_compl[1]:1 and lpcomp.comp[0]:1 alternate functions.
10 VSSD power_in Ground pin for the digital section.
11 NC unconnected No-connect pin on the 48-pin TQFP.
12 P3.0 bidirectional GPIO port 3 bit 0 with Smart I/O prgio[1].io[0], tcpwm.line[0]:0, SCB1 UART RX, I2C SCL and SPI MOSI alternate functions.
13 P3.1 bidirectional GPIO port 3 bit 1 with Smart I/O prgio[1].io[1], tcpwm.line_compl[0]:0, SCB1 UART TX, I2C SDA and SPI MISO alternate functions.
14 P3.2 bidirectional GPIO port 3 bit 2 with Smart I/O prgio[1].io[2], tcpwm.line[1]:0, SCB1 UART CTS, SPI clock and cpuss.swd_data (SWD data) alternate functions.
15 NC unconnected No-connect pin on the 48-pin TQFP.
16 P3.3 bidirectional GPIO port 3 bit 3 with Smart I/O prgio[1].io[3], tcpwm.line_compl[1]:0, SCB1 UART RTS, SPI select0 and cpuss.swd_clk (SWD clock) alternate functions.
17 P3.4 bidirectional GPIO port 3 bit 4 with Smart I/O prgio[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6] and SCB1 SPI select1 alternate functions.
18 P3.5 bidirectional GPIO port 3 bit 5 with Smart I/O prgio[1].io[5], tcpwm.line_compl[2]:0, tcpwm.tr_in[7] and SCB1 SPI select2 alternate functions.
19 P3.6 bidirectional GPIO port 3 bit 6 with Smart I/O prgio[1].io[6], tcpwm.line[3]:0, tcpwm.tr_in[8] and SCB1 SPI select3 alternate functions.
20 P3.7 bidirectional GPIO port 3 bit 7 with Smart I/O prgio[1].io[7], tcpwm.line_compl[3]:0, tcpwm.tr_in[9] and lpcomp.comp[1]:1 alternate functions.
21 VDDD power_in Power supply for the digital section.
22 P4.0 bidirectional GPIO port 4 bit 0 with csd.vref_ext analog function, SCB0 UART RX, I2C SCL and SPI MOSI, and tcpwm.tr_in[10].
23 P4.1 bidirectional GPIO port 4 bit 1 with csd.cshieldpads analog function, SCB0 UART TX, I2C SDA and SPI MISO, and tcpwm.tr_in[11].
24 P4.2 bidirectional GPIO port 4 bit 2 with csd.cmodpad analog function, SCB0 UART CTS, SPI clock and lpcomp.comp[0]:0.
25 P4.3 bidirectional GPIO port 4 bit 3 with csd.csh_tank analog function, SCB0 UART RTS, SPI select0 and lpcomp.comp[1]:0.
26 NC unconnected No-connect pin on the 48-pin TQFP.
27 NC unconnected No-connect pin on the 48-pin TQFP.
28 P0.0 bidirectional GPIO port 0 bit 0 with lpcomp.in_p[0], tcpwm.tr_in[0] and SCB0 SPI select1 alternate functions.
29 P0.1 bidirectional GPIO port 0 bit 1 with lpcomp.in_n[0], tcpwm.tr_in[1] and SCB0 SPI select2 alternate functions.
30 P0.2 bidirectional GPIO port 0 bit 2 with lpcomp.in_p[1] and SCB0 SPI select3 alternate functions.
31 P0.3 bidirectional GPIO port 0 bit 3 with lpcomp.in_n[1] analog function.
32 P0.4 bidirectional GPIO port 0 bit 4 with wco.wco_in (watch crystal), SCB1 UART RX, I2C SCL and SPI MOSI alternate functions.
33 P0.5 bidirectional GPIO port 0 bit 5 with wco.wco_out (watch crystal), SCB1 UART TX, I2C SDA and SPI MISO alternate functions.
34 P0.6 bidirectional GPIO port 0 bit 6 with srss.ext_clk, SCB1 UART CTS and SPI clock alternate functions.
35 P0.7 bidirectional GPIO port 0 bit 7 with SCB1 UART RTS and SPI select0 alternate functions.
36 XRES input External reset input pin.
37 VCCD power_out Regulated digital supply (1.8 V ± 5%); must be bypassed to ground with 0.1 µF (X5R ceramic or better) and connected to nothing else in the 1.8 V to 5.5 V supply mode.
38 VSSD power_in Ground pin for the digital section.
39 VDDD power_in Power supply for the digital section.
40 VDDA power_in Power supply for the analog section.
41 VSSA power_in Ground pin for the analog section.
42 P1.0 bidirectional GPIO port 1 bit 0 with tcpwm.line[2]:1, SCB0 UART RX, I2C SCL and SPI MOSI alternate functions.
43 P1.1 bidirectional GPIO port 1 bit 1 with tcpwm.line_compl[2]:1, SCB0 UART TX, I2C SDA and SPI MISO alternate functions.
44 P1.2 bidirectional GPIO port 1 bit 2 with tcpwm.line[3]:1, SCB0 UART CTS, tcpwm.tr_in[2] and SPI clock alternate functions.
45 P1.3 bidirectional GPIO port 1 bit 3 with tcpwm.line_compl[3]:1, SCB0 UART RTS, tcpwm.tr_in[3] and SPI select0 alternate functions.
46 P1.4 bidirectional GPIO port 1 bit 4 with SCB0 SPI select1 alternate function.
47 P1.5 bidirectional GPIO port 1 bit 5 with SCB0 SPI select2 alternate function.
48 P1.6 bidirectional GPIO port 1 bit 6 with SCB0 SPI select3 alternate function.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 21
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 21
GPIO voltage VGPIO_ABS -0.5 V Max is VDD + 0.5 21
Maximum current per GPIO IGPIO_ABS -25 25 mA 21
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin 21
ESD human body model ESD_HBM 2200 V 21
ESD charged device model ESD_CDM 500 V 21
Pin current for latch-up LU -140 140 mA 21
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Output voltage (for core logic) VCCD 1.8 V 22
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 22
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 22
Active mode current, CPU at 6 MHz IDD5 1.2 2 mA Execute from flash; CPU at 6 MHz 22
Active mode current, CPU at 24 MHz IDD8 2.4 4 mA Execute from flash; CPU at 24 MHz 22
Active mode current, CPU at 48 MHz IDD11 4.6 5.9 mA Execute from flash; CPU at 48 MHz 22
Sleep current, regulator on, 6 MHz IDD17 1.1 1.6 mA I2C wakeup WDT, and comparators on; 6 MHz 22
Sleep current, regulator on, 12 MHz IDD20 1.4 1.9 mA I2C wakeup, WDT, and comparators on; 12 MHz 22
Sleep current, regulator bypassed, 6 MHz IDD23 0.7 0.9 mA I2C wakeup, WDT, and Comparators on; 6 MHz 22
Sleep current, regulator bypassed, 12 MHz IDD23A 0.9 1.1 mA I2C wakeup, WDT, and Comparators on; 12 MHz 22
Deep Sleep current, VDD 1.8 V to 3.6 V IDD26 2.5 60 µA I2C wakeup and WDT on 22
Deep Sleep current, VDD 3.6 V to 5.5 V IDD29 2.5 60 µA I2C wakeup and WDT on 22
Deep Sleep current, regulator bypassed IDD32 2.5 60 µA I2C wakeup and WDT on 22
Supply current while XRES asserted IDD_XR 2 5 mA 22
IMO operating current at 48 MHz IIMO1 250 µA 39
IMO operating current at 24 MHz IIMO2 180 µA 39
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 39
IMO startup time TSTARTIMO 7 µs 39
ILO operating current IILO1 0.3 1.05 µA 40
ILO startup time TSTARTILO1 2 ms 40
ILO duty cycle TILODUTY 40 50 60 % 40
ILO frequency range FILOTRIM1 20 40 80 kHz 40
WCO crystal frequency FWCO 32.768 kHz 40
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 40
WCO equivalent series resistance ESR 50 kΩ 40
WCO drive level PD 1 µW 40
WCO startup time TSTART 500 ms 40
WCO crystal load capacitance CL 6 12.5 pF 40
WCO operating current (high power mode) IWCO1 8 µA 40
WCO operating current (low power mode) IWCO2 1 µA 40
External clock input frequency ExtClkFreq 0 48 MHz 41
External clock duty cycle ExtClkDuty 45 55 % measured at VDD/2 41
System clock source switching time TCLKSWITCH 3 4 Periods 41
Max delay added by Smart I/O in Bypass Mode PRG_BYPASS 1.6 ns 41
Operating ambient temperature TA -40 25 105 °C 44
Operating junction temperature TJ -40 125 °C 44
Package thermal resistance θJA TJA 73.5 °C/W 48LD TQFP 44
Package thermal resistance θJC TJC 33.5 °C/W 48LD TQFP 44

CAD (KiCad official)

  • Symbol: CY8C4025AZI-S413
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy8c4025azi-s413-etched.step / cy8c4025azi-s413-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4025azi-s413.step / cy8c4025azi-s413.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (58 pp, sha256 493ab905a29a5d98, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF