component

MAX31865AAP+T

Public Made by Adom

by adom

Analog Devices Inc Maxim Integrated Analog To Digital Converters (ADC), SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionmax31865aap+tfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

MAX31865AAP+T

Analog Devices Inc Maxim Integrated · Analog To Digital Converters (ADC) · SSOP-20-208mil

MAX31865AAP+T from Analog Devices Inc Maxim Integrated, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRDY output Active-low, push-pull data-ready output that goes low when a new conversion result is in the data register and returns high after a read of the RTD resistance data register.
2 DVDD power_in Digital supply voltage input; connect to a 3.3V supply and bypass to DGND with a 0.1µF capacitor.
3 VDD power_in Analog supply voltage input; connect to a 3.3V supply and bypass to GND1 with a 0.1µF capacitor.
4 BIAS power_out Bias voltage output (VBIAS) that can be disabled through the configuration register to reduce power dissipation when no conversions are running; connect to REFIN+.
5 REFIN+ input Positive reference voltage input; connect to BIAS and connect the reference resistor between REFIN+ and REFIN-.
6 REFIN- input Negative reference voltage input; connect the reference resistor between REFIN+ and REFIN-.
7 ISENSOR passive Low side of RREF; connect to REFIN-.
8 FORCE+ passive High-side RTD drive; connect to FORCE2 when using the 3-wire connection and is protected to ±45V.
9 FORCE2 passive Positive input used only in 3-wire mode; connect to FORCE+ for 3-wire, or to ground for 2-wire or 4-wire, and is protected to ±45V.
10 RTDIN+ input Positive RTD input, protected to ±45V.
11 RTDIN- input Negative RTD input, protected to ±45V.
12 FORCE- passive Low-side RTD return, protected to ±45V.
13 GND2 power_in Analog ground; connect to GND1.
14 SDI input Serial-data input for the SPI-compatible interface.
15 SCLK input Serial-data clock input for the SPI-compatible interface.
16 CS input Active-low chip select; set CS low to enable the serial interface.
17 SDO output Serial-data output for the SPI-compatible interface.
18 DGND power_in Digital ground.
19 GND1 power_in Analog ground; connect to GND2.
20 N.C. unconnected Do not connect.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package SSOP-20-208mil
Category Data Acquisition
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Voltage Range relative to GND1 (absolute max) VDD -0.3 4 V Relative to GND1 2
Voltage Range on BIAS, REFIN+, REFIN-, ISENSOR (absolute max) -0.3 V Upper limit printed as VDD + 0.3V 2
Voltage Range on FORCE+, FORCE2, FORCE-, RTDIN+, RTDIN- (absolute max) -50 50 V Relative to GND1 2
Voltage Range on DVDD (absolute max) DVDD -0.3 4 V Relative to DGND 2
Voltage Range on All Digital Pins (absolute max) -0.3 V Relative to DGND; upper limit printed as VDVDD + 0.3V 2
ESD Protection, all pins, Human Body Model -2 2 kV Human Body Model 2
Junction Temperature (absolute max) TJ 150 °C 2
Storage Temperature Range (absolute max) TSTG -65 150 °C 2
Soldering Temperature (reflow) (absolute max) 260 °C 2
Lead Temperature (soldering, 10s) (absolute max) 300 °C 10 s 2
Operating Temperature Range TA -40 125 °C 2
VDD Supply Voltage VDD 3 3.3 3.6 V TA = -40°C to +125°C 2
DVDD Supply Voltage VDVDD 3 3.3 3.6 V TA = -40°C to +125°C 2
Input Logic 0 (CS, SDI, SCLK) VIL -0.3 V Upper limit printed as 0.3 x VDVDD 2
Analog Voltages (FORCE+, FORCE2, FORCE-, RTDIN+, RTDIN-) 0 V Normal conversion results; upper limit printed as VBIAS 2
Cable Resistance RCABLE 0 50 Ω Per lead 2
ADC Resolution 15 bits No missing codes 2
ADC Common-Mode Input Range 0 V Upper limit printed as VBIAS 3
Input Leakage Current RTDIN+, RTDIN- 2 nA 0°C to +70°C, on-state 3
Input Leakage Current RTDIN+, RTDIN- 5 nA -40°C to +85°C, on-state 3
Input Leakage Current RTDIN+, RTDIN- 14 nA -40°C to +100°C, on-state 3
Bias Voltage VBIAS 1.95 2 2.06 V 3
Bias Voltage Output Current IOUT 0.2 5.75 mA 3
Bias Voltage Load Regulation 30 mV/mA IOUT ≤ 5.75mA 3
Bias Voltage Startup Time 10 ms Note 4 3
ADC Full-Scale Error -1 1 LSB 3
ADC Integral Nonlinearity -1 1 LSB Differential input, endpoint fit, 0.3 x VBIAS ≤ VREF ≤ VBIAS 3
ADC Offset Error -3 3 LSB 3
Power-Supply Current, Shutdown (Bias off, ADC off) IDD 1.5 3 mA Shutdown; Bias off, ADC off 3
Power-Supply Current, Bias on, active conversion IDD 2 3.5 mA Bias on, active conversion 3
Power-On Reset Voltage Threshold 2 2.27 V 3
Input Leakage Current, logic inputs IL -1 1 µA Logic inputs 3
Output Low Voltage VOL 0.4 V IOUT = 1.6mA 3
Data to SCLK Setup tDC 35 ns Notes 8, 9 4
SCLK to Data Hold tCDH 35 ns Notes 8, 9 4
SCLK to Data Valid tCDD 80 ns Notes 8, 9, 10 4
SCLK Low Time tCL 100 ns Note 9 4
SCLK High Time tCH 100 ns Note 9 4
SCLK Frequency tCLK 5 MHz Note 9 4
SCLK Rise and Fall tR, tF 200 ns Note 9 4
CS to SCLK Setup tCC 400 ns Note 9 4
SCLK to CS Hold tCCH 100 ns Note 9 4
CS Inactive Time tCWH 400 ns Note 9 4
CS to Output High-Z tCDZ 40 ns Notes 8, 9 4
Address 01h or 02h Decoded to DRDY High tDRDYH 50 ns After RTD register read access; Note 9 4
Temperature Conversion Time, continuous conversion (60Hz notch) tCONV 16.7 17.6 ms Continuous conversion (60Hz notch) 3
Temperature Conversion Time, single conversion (60Hz notch) tCONV 52 55 ms Single conversion (60Hz notch) 3
Temperature Conversion Time, single conversion (50Hz notch) tCONV 62.5 66 ms Single conversion (50Hz notch) 3
Temperature Conversion Time, continuous conversion (50Hz notch) tCONV 20 21 ms Continuous conversion (50Hz notch) 3
Automatic Fault Detection Cycle Time 550 600 µs From CS high to cycle complete 3
Power-Supply Rejection 1 LSB/V 3
Power-On Reset Voltage Hysteresis 120 mV 3
Input Capacitance, logic inputs CIN 6 pF Logic inputs 3
ADC Noise (over Nyquist Bandwidth) 150 µV RMS Input referred 3
Common-Mode Rejection 90 dB 3
50/60Hz Noise Rejection 82 dB Fundamental and harmonics 3

CAD (KiCad official)

  • Symbol: MAX31865AAP+T
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: max31865aap-t-etched.step / max31865aap-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max31865aap-t.step / max31865aap-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (26 pp, sha256 88f540410eb8c2ac, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF