XL1050 from XINLUDA, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXD	input	Transmit data input from the CAN controller. Logic low drives the bus to the dominant state; logic high (or floating) leaves the bus in the recessive state. VIH min 2 V, VIL max 0.8 V. A built-in dominant time-out disables the driver if TXD is held low longer than tdom (300-700 µs).
2	GND	power_in	Ground / supply return.
3	VCC	power_in	Supply voltage. Nominal 5 V (operating 4.5 V-5.5 V, absolute max 6 V). Decouple locally to GND.
4	RXD	output	Receive data output to the CAN controller; reports the bus state. Low = dominant, High = recessive. Push-pull CMOS output (VOH ≥ 4 V at IO = -2 mA, VOL ≤ 0.4 V at IO = 2 mA).
5	Vref	output	Reference voltage output, nominally 0.5·VCC (0.4·VCC to 0.6·VCC) for
6	CANL	bidirectional	Low-level CAN bus line. Driven low (~1.5 V) in dominant state, biased to ~0.5·VCC in recessive state. Bus-side absolute rating -60 V to +60 V; protected against automotive transients (±200 V).
7	CANH	bidirectional	High-level CAN bus line. Driven high (~3.5 V) in dominant state, biased to ~0.5·VCC in recessive state. Bus-side absolute rating -60 V to +60 V; protected against automotive transients (±200 V).
8	S	input	Mode select. Low (or grounded) selects high-speed mode (normal operation); High (tied to VCC) selects silent mode with the transmitter disabled. Pin is high-impedance / defaults to silent if left floating; grounding is recommended for high-speed-only applications.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	SOIC-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

XL1050

CAD (KiCad official)

Symbol: XL1050
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`xl1050.step`	122 KB	You want the bare part, or you mark your own boards.
`xl1050-etched.step`	1.4 MB	You want the part with `XL1050` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 355 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (13 pp, sha256 4a9c705f2257e80c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF