component
UC3845ADTR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUC3845ADTR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-14
UC3845ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Low-impedance 1 MHz internal error amplifier output, also the input to the peak current limit / PWM comparator, with 80 dB open-loop gain (AVOL); maximum sink current is 6 mA and it is not internally current-limited. |
| 2 | NC | unconnected | No internal connection. |
| 3 | FB | input | Error amplifier input used to close the converter voltage feedback loop and set stability. |
| 4 | NC | unconnected | No internal connection. |
| 5 | ISENSE | input | Input to the peak current limit / PWM comparator; the maximum peak current-sense signal is internally clamped at 1 V. |
| 6 | NC | unconnected | No internal connection. |
| 7 | RT/CT | input | Internal oscillator timing input programmed with external RT and CT; TI recommends CT of 470 pF to 4.7 nF and RT of 5 kΩ to 100 kΩ. |
| 8 | PGND | power_in | Power ground and gate-driver return path, allowing a star-ground layout that keeps gate-driver return current away from the signal GND pin. |
| 9 | GND | power_in | Controller signal ground. |
| 10 | OUTPUT | output | 1 A totem-pole gate driver output that can source and sink up to 1 A; a gate driver resistor must be used to limit gate-driver current. |
| 11 | VC | input | Gate driver bias input; a bias capacitor at least 10 times the gate capacitance of the main switching FET must be placed on this pin. |
| 12 | VCC | power_in | Gate driver bias supply input (recommended VCC minimum 11 V, absolute maximum 30 V); a bias capacitor at least 10 times the gate capacitance of the main switching FET must be placed on this pin. |
| 13 | NC | unconnected | No internal connection. |
| 14 | VREF | power_in | PWM controller voltage reference output that must supply no more than 10 mA in normal operation, is short-circuit protected at about 100 mA, and requires a 1 µF high-frequency bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
UC3845ADTR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
uc3845adtr-etched.step/uc3845adtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc3845adtr.step/uc3845adtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
1f5ad8805f414728, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).