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CD4073BM

Public Made by Adom

by adom

HGSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CD4073BM

HGSEMI · Logic Gates · SOP-14

CD4073BM from HGSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Gate input A of the CD4073B triple AND gate; CMOS input protected, input voltage limited to -0.5 V to +0.5 V per the ratings table.
2 B input Gate input B of the CD4073B triple AND gate; CMOS input protected, maximum input current 1 µA at 18 V over temperature.
3 D input Gate input D of the CD4073B triple AND gate; CMOS input protected, maximum DC input current 10 mA.
4 E input Gate input E of the CD4073B triple AND gate; CMOS input protected, input capacitance 5 pF typ.
5 F input Gate input F of the CD4073B triple AND gate; CMOS input protected, input capacitance 7.5 pF max.
6 K output Gate output K of the CD4073B, with standardized symmetrical output characteristics (VOL max 0.05 V, VOH min 4.95 V at VDD=5 V).
7 VSS power_in Ground / negative supply terminal; all voltages are referenced to VSS.
8 C input Gate input C of the CD4073B triple AND gate; CMOS input protected, VIL max 1.5 V and VIH min 3.5 V at VDD=5 V.
9 J output Gate output J of the CD4073B, with propagation delay typ. 60 ns at VDD=10 V.
10 L output Gate output L of the CD4073B, with standardized symmetrical output characteristics and transition time typ. 50 ns at VDD=10 V.
11 I input Gate input I of the CD4073B triple AND gate; CMOS input protected, noise margin 1 V at VDD=5 V.
12 H input Gate input H of the CD4073B triple AND gate; CMOS input protected, noise margin 2 V at VDD=10 V.
13 G input Gate input G of the CD4073B triple AND gate; CMOS input protected, noise margin 2.5 V at VDD=15 V.
14 VDD power_in Positive supply; recommended 5 V to 15 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply-Voltage Range (for full package temperature range) 5 15 V For T=Full Package Temperature Range 5
Operating-Temperature Range TA -40 85 ℃ 4
DC supply-voltage range VDD -0.5 20 V Voltages referenced to VSS terminal 4
Input voltage range, all inputs -0.5 0.5 V 4
DC input current, any one input 10 mA Any one input 4
Power dissipation per package (PD) PD 500 mA For TA=55℃ to +100℃ 4
Power dissipation per package (PD), derated range PD 200 mW For TA=+100℃ to +125℃ (Derate Linearly at) 12 4
Quiescent Device Current IDD IDD 0.25 µA VDD=5 V; TA=-40℃ 5
Quiescent Device Current IDD IDD 7.5 µA VDD=5 V; TA=+85℃ 5
Quiescent Device Current IDD IDD 0.01 0.25 µA VDD=5 V; TA=+25℃ 5
Quiescent Device Current IDD IDD 0.5 µA VDD=10 V; TA=-40℃ 5
Quiescent Device Current IDD IDD 15 µA VDD=10 V; TA=+85℃ 5
Quiescent Device Current IDD IDD 0.01 0.5 µA VDD=10 V; TA=+25℃ 5
Quiescent Device Current IDD IDD 1 µA VDD=15 V; TA=-40℃ 5
Quiescent Device Current IDD IDD 30 µA VDD=15 V; TA=+85℃ 5
Quiescent Device Current IDD IDD 0.01 1 µA VDD=15 V; TA=+25℃ 5
Quiescent Device Current IDD IDD 5 µA VDD=20 V; TA=-40℃ 5
Quiescent Device Current IDD IDD 150 µA VDD=20 V; TA=+85℃ 5
Quiescent Device Current IDD IDD 0.02 5 µA VDD=20 V; TA=+25℃ 5
Output Low (Sink) Current IOL IOL 0.61 mA VO=0.4 V; VDD=5 V; TA=-40℃ 5
Output Low (Sink) Current IOL IOL 0.42 mA VO=0.4 V; VDD=5 V; TA=+85℃ 5
Output Low (Sink) Current IOL IOL 0.51 1 mA VO=0.4 V; VDD=5 V; TA=+25℃ 5
Output Low (Sink) Current IOL IOL 1.5 mA VO=0.5 V; VDD=10 V; TA=-40℃ 5
Output Low (Sink) Current IOL IOL 1.1 mA VO=0.5 V; VDD=10 V; TA=+85℃ 5
Output Low (Sink) Current IOL IOL 1.3 2.6 mA VO=0.5 V; VDD=10 V; TA=+25℃ 5
Output Low (Sink) Current IOL IOL 4 mA VO=1.5 V; VDD=15 V; TA=-40℃ 5
Output Low (Sink) Current IOL IOL 2.8 mA VO=1.5 V; VDD=15 V; TA=+85℃ 5
Output Low (Sink) Current IOL IOL 3.4 6.8 mA VO=1.5 V; VDD=15 V; TA=+25℃ 5
Output High (Source) Current IOH IOH -0.61 mA VO=4.6 V; VDD=5 V; TA=-40℃ 5
Output High (Source) Current IOH IOH -0.42 mA VO=4.6 V; VDD=5 V; TA=+85℃ 5
Output High (Source) Current IOH IOH -0.51 -1 mA VO=4.6 V; VDD=5 V; TA=+25℃ 5
Output High (Source) Current IOH IOH -1.8 mA VO=2.5 V; VDD=5 V; TA=-40℃ 5
Output High (Source) Current IOH IOH -1.3 mA VO=2.5 V; VDD=5 V; TA=+85℃ 5
Output High (Source) Current IOH IOH -1.6 -3.2 mA VO=2.5 V; VDD=5 V; TA=+25℃ 5
Output High (Source) Current IOH IOH -1.5 mA VO=9.5 V; VDD=10 V; TA=-40℃ 5
Output High (Source) Current IOH IOH -1.1 mA VO=9.5 V; VDD=10 V; TA=+85℃ 5
Output High (Source) Current IOH IOH -1.3 -2.6 mA VO=9.5 V; VDD=10 V; TA=+25℃ 5
Output High (Source) Current IOH IOH -4 mA VO=13.5 V; VDD=10 V as printed; TA=-40℃ 5
Output High (Source) Current IOH IOH -2.8 mA VO=13.5 V; VDD=10 V as printed; TA=+85℃ 5
Output High (Source) Current IOH IOH -3.4 -6.8 mA VO=13.5 V; VDD=10 V as printed; TA=+25℃ 5
Output Voltage Low-Level VOL VOL 0 0.05 V VDD=5 V 5
Output Voltage High-Level VOH VOH 4.95 5 V VDD=5 V 5
Output Voltage High-Level VOH VOH 9.95 10 V VDD=10 V 5
Output Voltage High-Level VOH VOH 14.95 15 V VDD=15 V 5
Input Low Voltage VIL VIL 1.5 V VO=0.5 V; VDD=5 V 5
Input Low Voltage VIL VIL 3 V VO=1 V; VDD=10 V 5
Input Low Voltage VIL VIL 4 V VO=1.5 V; VDD=15 V 5
Input High Voltage VIH VIH 3.5 V VDD=5 V 5
Input High Voltage VIH VIH 7 V VDD=10 V 5
Input High Voltage VIH VIH 11 V VDD=15 V 5
Input Current IIN IIN -1 1 µA VDD=18 V (table header printed '0.18 18') 5
Propagation Delay Time TPHL,TPLH TPHL,TPLH 125 250 NS VDD=5 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Propagation Delay Time TPHL,TPLH TPHL,TPLH 60 120 NS VDD=10 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Propagation Delay Time TPHL,TPLH TPHL,TPLH 40 90 NS VDD=15 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Transition Time TPHL,TPLH TPHL,TPLH 100 200 NS VDD=5 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Transition Time TPHL,TPLH TPHL,TPLH 50 100 NS VDD=10 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Transition Time TPHL,TPLH TPHL,TPLH 40 80 NS VDD=15 V; TA=25ºC; input tr,tf=20 ns; CL=50 pf; RL=200KΩ 5
Input Capacitance CIN CIN 5 7.5 Pf Any input 5

CAD (KiCad official)

  • Symbol: CD4073BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4073bm-etched.step / cd4073bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4073bm.step / cd4073bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (11 pp, sha256 05467aba098f95c2, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF