component
TPS73130MDBVREP
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS73130MDBVREP
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS73130MDBVREP from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Unregulated input supply to the regulator, with an input voltage range of 1.7 V to 5.5 V and an absolute maximum VIN range of -0.3 V to 6 V. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | EN | input | Driving EN high turns on the regulator and driving it low puts the regulator into shutdown mode; EN can be connected to IN if not used, and its absolute maximum range is -0.3 V to 6 V. |
| 4 | NR | passive | For fixed voltage versions only, connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. |
| 5 | OUT | power_out | Output of the regulator, with no output capacitor requirements for stability and an output voltage range of 1.2 V to 5 V for fixed versions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.7 | 5.5 | V | 4 | ||
| Output voltage accuracy, nominal TA = 25°C | VOUT | -0.5 | 0.5 | % | TA = 25°C | 4 | |
| Output voltage accuracy over line, load and temperature | VOUT | -1 | 1 | % | VOUT + 0.5 V ≤ VIN ≤ 5.5 V, 10 mA ≤ IOUT ≤ 150 mA | 4 | |
| Dropout voltage | VDO | 30 | 100 | mV | IOUT = 150 mA (VIN = VOUT (nom), 0.1 V) | 4 | |
| Output current limit | ICL | 150 | 360 | 500 | mA | VOUT = 0.9 × VOUT(nom) | 4 |
| Reverse leakage current | IREV | 0.1 | 15 | μA | VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT | 4 | |
| Ground pin current at IOUT = 10 mA | IGND | 400 | 550 | μA | IOUT = 10 mA (IQ) | 4 | |
| Ground pin current at IOUT = 150 mA | IGND | 550 | 750 | μA | IOUT = 150 mA | 4 | |
| Shutdown current | ISHDN | 0.02 | 1 | μA | VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V | 4 | |
| Enable high voltage | VEN(HI) | 1.7 | V | Enable high (enabled) | 4 | ||
| Enable low voltage | VEN(LO) | 0 | 0.5 | V | Enable low (shutdown) | 4 | |
| Enable pin current (enabled) | IEN(HI) | 0.02 | 0.1 | μA | VEN = 5.5 V | 4 | |
| Operating ambient temperature | TA | -55 | 125 | °C | 4 | ||
| Power-supply rejection ratio at 100 Hz | PSRR | 58 | dB | f = 100 Hz, IOUT = 150 mA | 4 | ||
| Power-supply rejection ratio at 10 kHz | PSRR | 37 | dB | f = 10 kHz, IOUT = 150 mA | 4 | ||
| Thermal shutdown temperature, shutdown | TSD | 160 | °C | Shutdown, temperature increasing | 4 | ||
| Thermal shutdown temperature, reset | TSD | 140 | °C | Reset, temperature decreasing | 4 | ||
| Input voltage (absolute maximum) | VIN | -0.3 | 6 | V | Over operating junction temperature range | 3 | |
| Enable voltage (absolute maximum) | VEN | -0.3 | 6 | V | Over operating junction temperature range | 3 | |
| Output voltage (absolute maximum) | VOUT | -0.3 | 5.5 | V | Over operating junction temperature range | 3 | |
| Ambient temperature range (absolute maximum) | TA | -55 | 150 | °C | Over operating junction temperature range | 3 | |
| Storage temperature range | TSTG | -65 | 150 | °C | 3 | ||
| ESD rating, HBM | ESD | 2 | kV | HBM | 3 | ||
| ESD rating, CDM | ESD | 500 | V | CDM | 3 | ||
| Junction-to-ambient thermal resistance, low-K board | RΘJA | 255 | °C/W | DBV package, JEDEC Low-K (1s) board | 3 | ||
| Junction-to-ambient thermal resistance, high-K board | RΘJA | 180 | °C/W | DBV package, JEDEC High-K (2s2p) board | 3 | ||
| Junction-to-case thermal resistance | RΘJC | 64 | °C/W | DBV package | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | out of the IN pin due to voltage applied on the OUT boards are shown in the Power Dissipation Ratings pin. There is additional current flowing into the OUT table. Using heavier copper increases the | 15 |
CAD (KiCad official)
- Symbol:
TPS73130MDBVREP - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps73130mdbvrep-etched.step/tps73130mdbvrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps73130mdbvrep.step/tps73130mdbvrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
095d3e44c142baf2, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).