component
SN74HC4020DR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSN74HC4020DR
Texas Instruments · Counters, Dividers · SOIC-16
SN74HC4020DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QL | output | Stage-12 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 2 | QM | output | Stage-13 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 3 | QN | output | Stage-14 (MSB) binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 4 | QF | output | Stage-6 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 5 | QE | output | Stage-5 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 6 | QG | output | Stage-7 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 7 | QD | output | Stage-4 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 8 | GND | power_in | Ground reference (0 V); continuous current through GND pin ±50 mA absolute maximum. |
| 9 | QA | output | Stage-1 (LSB, ÷2) binary counter output; propagation delay from CLK = 16 ns typ at VCC = 4.5 V, CL = 50 pF; forced low when CLR is high. |
| 10 | CLK | input | Clock input; counter advances on negative-going (falling) edge; maximum clock frequency 28 MHz typ at VCC = 4.5 V. |
| 11 | CLR | input | Asynchronous active-high clear input; resets all outputs low independently of CLK; minimum pulse width 14 ns at VCC = 4.5 V. |
| 12 | QI | output | Stage-9 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 13 | QH | output | Stage-8 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 14 | QJ | output | Stage-10 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 15 | QK | output | Stage-11 binary counter output; advances on negative-going CLK edge; forced low (asynchronously) when CLR is high. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; ICC max 80 µA at VCC = 6 V, IO = 0. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74HC4020DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc4020dr-etched.step/sn74hc4020dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc4020dr.step/sn74hc4020dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
9fd6b45c812cd24c, retrieved 2026-09-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).