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CD4098BE
Public Made by Adomby adom
Texas Instruments Monostable Multivibrators, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4098BE
Texas Instruments · Monostable Multivibrators · DIP-16
CD4098BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CX1 | passive | External timing capacitor terminal for MONO1, electrically connected internally to pins 8 and 15 (VSS). |
| 2 | RXCX(1) | passive | Junction of external timing resistor RX and capacitor CX for MONO1 (RX minimum 5 kΩ, CX maximum 100 µF). |
| 3 | RESET(1) | input | Active-low reset input of MONO1 that immediately terminates the output pulse; tie to VDD if unused, or to VSS if the whole section is unused. |
| 4 | +TR(1) | input | Leading-edge trigger input of MONO1; tie to VSS if unused. |
| 5 | -TR(1) | input | Trailing-edge trigger input of MONO1; tie to VDD if unused. |
| 6 | Q1 | output | Buffered Q output of MONO1. |
| 7 | Q1̅ | output | Buffered complementary Q-bar output of MONO1. |
| 8 | VSS | power_in | Ground (negative supply) terminal, electrically connected internally to pins 1 and 15. |
| 9 | Q2̅ | output | Buffered complementary Q-bar output of MONO2. |
| 10 | Q2 | output | Buffered Q output of MONO2. |
| 11 | -TR(2) | input | Trailing-edge trigger input of MONO2; tie to VDD if unused. |
| 12 | +TR(2) | input | Leading-edge trigger input of MONO2; tie to VSS if unused. |
| 13 | RESET(2) | input | Active-low reset input of MONO2 that immediately terminates the output pulse; tie to VDD if unused, or to VSS if the whole section is unused. |
| 14 | RXCX(2) | passive | Junction of external timing resistor RX and capacitor CX for MONO2 (RX minimum 5 kΩ, CX maximum 100 µF). |
| 15 | CX2 | passive | External timing capacitor terminal for MONO2, electrically connected internally to pins 1 and 8 (VSS). |
| 16 | VDD | power_in | Positive supply terminal; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4098BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4098be-etched.step/cd4098be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4098be.step/cd4098be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
699241f92bb31789, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).