component
CD74HC195PWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownCD74HC195PWR
Texas Instruments · Shift Registers · TSSOP-16
CD74HC195PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous Master Reset, active low; a Low sets all Q outputs Low (Q3 bar High) independent of any other input. |
| 2 | J | input | Serial J input to the first stage, used when PE is High; tie to K for a D-type input. |
| 3 | K | input | Serial K input to the first stage, used when PE is High; tie to J for a D-type input. |
| 4 | D0 | input | Parallel data input 0, transferred to Q0 on the Low-to-High clock transition when PE is Low. |
| 5 | D1 | input | Parallel data input 1, transferred to Q1 on the Low-to-High clock transition when PE is Low. |
| 6 | D2 | input | Parallel data input 2, transferred to Q2 on the Low-to-High clock transition when PE is Low. |
| 7 | D3 | input | Parallel data input 3, transferred to Q3 on the Low-to-High clock transition when PE is Low. |
| 8 | GND | power_in | Ground (0V) supply pin. |
| 9 | PE | input | Parallel Enable; High selects shift right via J and K, Low selects parallel load from D0-D3 on the clock edge. |
| 10 | CP | input | Clock pulse input; all synchronous transfers occur on the Low-to-High transition. |
| 11 | Q3 bar | output | Complementary output of the last stage (inverse of Q3). |
| 12 | Q3 | output | Last-stage register output Q3. |
| 13 | Q2 | output | Register output Q2. |
| 14 | Q1 | output | Register output Q1. |
| 15 | Q0 | output | First-stage register output Q0. |
| 16 | VCC | power_in | Positive supply voltage, 2V to 6V for HC types (absolute max -0.5V to 7V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD74HC195PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hc195pwr-etched.step/cd74hc195pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc195pwr.step/cd74hc195pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
5004546e382e462d, retrieved 2026-10-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).