component
NCP5106BDR2G
Public Made by Adomby adom
onsemi Gate Drivers, SOIC-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownNCP5106BDR2G
onsemi · Gate Drivers · SOIC-8-150mil
NCP5106BDR2G from onsemi, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low side and main power supply, with a gate drive supply range of 10 V to 20 V and an absolute maximum of −0.3 to 20 V (23 V transient at 5 mA for 10 ms). |
| 2 | IN_HI | input | Logic input for the high side driver with output in phase, with a low level threshold of 0.8 V max and a high level threshold of 2.3 V min, and allowed input range of −1.0 V to VCC + 0.3 V. |
| 3 | IN_LO | input | Logic input for the low side driver with output in phase, with a low level threshold of 0.8 V max and a high level threshold of 2.3 V min, and allowed input range of −1.0 V to VCC + 0.3 V. |
| 4 | GND | power_in | Ground reference pin for the device. |
| 5 | DRV_LO | output | Low side gate drive output, with 250 mA source and 500 mA sink pulsed short-circuit current capability and an output voltage range of −0.3 V to VCC + 0.3 V. |
| 6 | BRIDGE | power_in | Bootstrap return or high side floating supply return, rated −1 V to 600 V (VHV) and tolerating a negative bridge voltage of −10 V for IN_LO signal propagation. |
| 7 | DRV_HI | output | High side gate drive output, with an output voltage range of VBRIDGE − 0.3 V to VBOOT + 0.3 V. |
| 8 | VBOOT | power_in | Bootstrap power supply for the high side floating supply, with VBOOT−VBRIDGE rated −0.3 V to 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8-150mil |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Main power supply voltage | VCC | -0.3 | 20 | V | 4 | ||
| Main transient power supply voltage | VCC_transient | 23 | V | IVCC_max = 5 mA during 10 ms | 4 | ||
| VHV: High voltage BRIDGE pin | VBRIDGE | -1 | 600 | V | 4 | ||
| Allowable negative bridge pin voltage for IN_LO signal propagation to DRV_LO | VBRIDGE | -10 | V | see characterization curves for detailed results | 4 | ||
| VHV: Floating supply voltage | VBOOT-VBRIDGE | -0.3 | 20 | V | 4 | ||
| Low side output voltage | VDRV_LO | -0.3 | V | 4 | |||
| Allowable output slew rate | dVBRIDGE/dt | 50 | V/ns | 4 | |||
| Inputs IN_HI, IN_LO | VIN_XX | -1 | V | 4 | |||
| ESD capability HBM model | ESD | 2 | kV | HBM model, all pins except pins 6-7-8 in 8 pins package | 4 | ||
| ESD capability Machine model | ESD | 200 | V | Machine model, all pins except pins 6-7-8 in 8 pins package | 4 | ||
| Storage Temperature Range | TST | -55 | 150 | °C | 4 | ||
| Maximum Operating Junction Temperature | TJ_max | 150 | °C | 4 | |||
| VCC UV Start-up voltage threshold | VCC_stup | 8 | 8.9 | 9.9 | V | 5 | |
| VCC UV Shut-down voltage threshold | VCC_shtdwn | 7.3 | 8.2 | 9.1 | V | 5 | |
| Hysteresis on VCC | VCC_hyst | 0.3 | 0.7 | V | 5 | ||
| Vboot Start-up voltage threshold reference to bridge pin | Vboot_stup | 8 | 8.9 | 9.9 | V | Vboot_stup = Vboot − Vbridge | 5 |
| Vboot UV Shut-down voltage threshold | Vboot_shtdwn | 7.3 | 8.2 | 9.1 | V | 5 | |
| Hysteresis on Vboot | Vboot_hyst | 0.3 | 0.7 | V | 5 | ||
| Low level input voltage threshold | VIN | 0.8 | V | 5 | |||
| High level input voltage threshold | VIN | 2.3 | V | 5 | |||
| Logic “1” input bias current | IIN+ | 5 | 25 | µA | @ VIN_XX = 5 V @ 25°C | 5 | |
| Logic “0” input bias current | IIN− | 2 | µA | @ VIN_XX = 0 V @ 25°C | 5 | ||
| Output resistor (Typical value @ 25°C) Source | ROH | 30 | 60 | Ω | Typical value @ 25°C | 5 | |
| Output resistor (Typical value @ 25°C) Sink | ROL | 10 | 20 | Ω | Typical value @ 25°C | 5 | |
| High level output voltage, VBIAS−VDRV_XX | VDRV_H | 0.7 | 1.6 | V | @ IDRV_XX = 20 mA | 5 | |
| Low level output voltage | VDRV_L | 0.2 | 0.6 | V | @ IDRV_XX = 20 mA | 5 | |
| Turn-on propagation delay | tON | 100 | 170 | ns | Vbridge = 0 V | 5 | |
| Turn-off propagation delay | tOFF | 100 | 170 | ns | Vbridge = 0 V or 50 V (Note 2) | 5 | |
| Output voltage rise time (from 10% to 90%) | tr | 85 | 160 | ns | @ VCC = 15 V with 1 nF load | 5 | |
| Output voltage fall time (from 90% to 10%) | tf | 35 | 75 | ns | @ VCC = 15 V with 1 nF load | 5 | |
| Propagation delay matching between the High side and the Low side | t | 20 | 35 | ns | @ 25°C (Note 3) | 5 | |
| Internal fixed dead time (only valid for B version) | DT | 65 | 100 | 190 | ns | Version B (Note 4) | 5 |
| Minimum input width that changes the output | tPW1 | 50 | ns | 5 | |||
| Maximum input width that does not change the output (SOIC-8, PDIP-8) | tPW2 | 20 | ns | SOIC-8, PDIP-8 package | 5 | ||
| Leakage current on high voltage pins to GND | IHV_LEAK | 5 | 40 | µA | VBOOT = VBRIDGE = DRV_HI = 600 V | 5 | |
| Consumption in active mode | ICC1 | 4 | 5 | mA | VCC = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs | 5 | |
| Consumption in inhibition mode | ICC2 | 250 | 400 | µA | VCC = Vboot | 5 | |
| Output high short circuit pulsed current | IDRVsource | 250 | mA | VDRV = 0 V, PW 10 s (Note 1) | 5 | ||
| Output low short circuit pulsed current | IDRVsink | 500 | mA | VDRV = VCC, PW 10 s (Note 1) | 5 | ||
| Input pull-down resistor | RIN | 200 | kΩ | VIN < 0.5 V | 5 | ||
| VCC current consumption in inhibition mode | ICC3 | 200 | µA | 5 | |||
| Vboot current consumption in inhibition mode | ICC4 | 50 | µA | 5 | |||
| Junction-to-Air thermal resistance, SO-8 | RθJA | 178 | °C/W | Junction-to-Air | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | voltage applied to the bridge pin thus corresponds to the forward voltage of the body diode. However, as pcb copper | 16 |
CAD (KiCad official)
- Symbol:
NCP5106BDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
- 3D model files:
ncp5106bdr2g-etched.step/ncp5106bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp5106bdr2g.step/ncp5106bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (19 pp, sha256
366362eb0816348f, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).