component
TMS320F28031PAGQ
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28031PAGQ
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
TMS320F28031PAGQ from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | General-purpose I/O 22 with alternate functions eQEP1 strobe (I/O) and LIN transmit (O); GPIO function is the reset default and the internal pull-up is enabled after reset. |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with alternate functions I2C-A data (open-drain I/OD), ePWM external sync input and ADC start-of-conversion A output. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with alternate functions I2C-A clock (open-drain I/OD), ePWM external sync output and ADC start-of-conversion B output. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | General-purpose I/O 23 with alternate functions eQEP1 index (I/O) and LIN receive (I). |
| 5 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground, as close to the pin as possible. |
| 6 | VSS | power_in | Digital ground pin. |
| 7 | XRS | bidirectional | Device reset input and watchdog reset output with internal pull-up (open-drain output); driven low on power-up, brown-out and watchdog reset, and a 2.2 kΩ to 10 kΩ resistor is to be placed between XRS and VDDIO. |
| 8 | TRST | input | JTAG test reset input with internal pull-down; must be held low during normal device operation, and an external pull-up (typically 2.2 kΩ) is required on this pin. |
| 9 | ADCINA7 | input | ADC group A, channel 7 analog input. |
| 10 | ADCINA6/COMP3A/AIO6 | bidirectional | ADC group A, channel 6 analog input, also comparator 3A input and digital AIO6 (I/O); AIO pins have no internal pull-up. |
| 11 | ADCINA4/COMP2A/AIO4 | bidirectional | ADC group A, channel 4 analog input, also comparator 2A input and digital AIO4 (I/O); AIO pins have no internal pull-up. |
| 12 | ADCINA3 | input | ADC group A, channel 3 analog input. |
| 13 | ADCINA2/COMP1A/AIO2 | bidirectional | ADC group A, channel 2 analog input, also comparator 1A input and digital AIO2 (I/O); AIO pins have no internal pull-up. |
| 14 | ADCINA1 | input | ADC group A, channel 1 analog input. |
| 15 | ADCINA0/VREFHI | input | ADC group A, channel 0 analog input; this pin is shared with VREFHI (external ADC reference high, used only in external reference mode, must not exceed VDDA) and the two functions cannot be used at the same time. |
| 16 | VDDA | power_in | Analog power supply pin; place a 2.2 µF capacitor (typical) near this pin. |
| 17 | VSSA/VREFLO | power_in | Analog ground pin; ADC external reference low (VREFLO) is always tied to VSSA on the 64-pin PAG device. |
| 18 | ADCINB0 | input | ADC group B, channel 0 analog input. |
| 19 | ADCINB1 | input | ADC group B, channel 1 analog input. |
| 20 | ADCINB2/COMP1B/AIO10 | bidirectional | ADC group B, channel 2 analog input, also comparator 1B input and digital AIO10 (I/O); AIO pins have no internal pull-up. |
| 21 | ADCINB3 | input | ADC group B, channel 3 analog input. |
| 22 | ADCINB4/COMP2B/AIO12 | bidirectional | ADC group B, channel 4 analog input, also comparator 2B input and digital AIO12 (I/O); AIO pins have no internal pull-up. |
| 23 | ADCINB6/COMP3B/AIO14 | bidirectional | ADC group B, channel 6 analog input, also comparator 3B input and digital AIO14 (I/O); AIO pins have no internal pull-up. |
| 24 | ADCINB7 | input | ADC group B, channel 7 analog input. |
| 25 | GPIO31/CANTXA | bidirectional | General-purpose I/O 31 with alternate function eCAN-A transmit (O). |
| 26 | GPIO30/CANRXA | bidirectional | General-purpose I/O 30 with alternate function eCAN-A receive (I). |
| 27 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 with alternate functions SCI-A transmit (O), I2C-A clock (open-drain I/OD) and trip-zone input 3 (I). |
| 28 | VSS | power_in | Digital ground pin. |
| 29 | VDDIO | power_in | Digital I/O buffer and flash power pin; a decoupling capacitor is to be placed on each VDDIO pin, with the value set by the system voltage regulation solution (recommended 2.97 V to 3.63 V). |
| 30 | TEST2 | unconnected | Test pin reserved for TI; must be left unconnected. |
| 31 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | General-purpose I/O 9 with alternate functions ePWM5B output (O), LIN transmit A (O) and high-resolution capture 1 input (I). |
| 32 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with alternate functions SCI receive (I), I2C-A data (open-drain I/OD) and trip-zone input 2 (I). |
| 33 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | General-purpose I/O 18 with alternate functions SPI-A clock (I/O), LIN transmit (O) and XCLKOUT (O/Z, derived from SYSCLKOUT; reset default XCLKOUT = SYSCLKOUT/4). |
| 34 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with alternate functions SPI-A slave output/master input (I/O) and trip-zone input 3 (I). |
| 35 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8 with alternate functions ePWM5A output with HRPWM channel (O) and ADC start-of-conversion A output (O). |
| 36 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 with alternate functions SPI-A slave input/master output (I/O) and trip-zone input 2 (I). |
| 37 | GPIO12/TZ1/SCITXDA/SPISIMOB | bidirectional | General-purpose I/O 12 with alternate functions trip-zone input 1 (I), SCI-A transmit (O) and SPI-B slave input/master output (I/O). |
| 38 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with alternate functions ePWM4B output (O) and SCI-A receive (I). |
| 39 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with alternate functions ePWM4A output with HRPWM channel (O), external ePWM sync input (I) and external ePWM sync output (O). |
| 40 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator must be connected between X1 and X2, and X2 is to be left unconnected if not used. |
| 41 | X1 | input | 1.8 V on-chip crystal oscillator input; must not be driven with a 3.3 V level, must be connected to GND if unused, and the XCLKIN path must be disabled via CLKCTL when a crystal is used. |
| 42 | VSS | power_in | Digital ground pin. |
| 43 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground. |
| 44 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | General-purpose I/O 19 with alternate functions external oscillator input XCLKIN (I), SPI-A slave transmit enable (I/O), LIN receive (I) and enhanced capture 1 (I/O); the XCLKIN path is not controlled by this pin's mux. |
| 45 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38 with JTAG test clock TCK (I, internal pull-up) and alternate external oscillator input XCLKIN (I); the default XCLKIN source selection is GPIO38. |
| 46 | GPIO37/TDO | tri_state | General-purpose I/O 37 with JTAG test data output TDO (O/Z, 8 mA drive), which is shifted out on the falling edge of TCK. |
| 47 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input TDI (I, internal pull-up), clocked on the rising edge of TCK. |
| 48 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test mode select TMS (I, internal pull-up), clocked on the rising edge of TCK. |
| 49 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | General-purpose I/O 11 with alternate functions ePWM6B output (O), LIN receive A (I) and high-resolution capture 2 input (I). |
| 50 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5 with alternate functions ePWM3B output (O), SPI-A slave input/master output (I/O) and enhanced capture 1 (I/O). |
| 51 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with alternate function ePWM3A output with HRPWM channel (O). |
| 52 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10 with alternate functions ePWM6A output with HRPWM channel (O) and ADC start-of-conversion B output (O). |
| 53 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | General-purpose I/O 3 with alternate functions ePWM2B output (O), SPI-A slave output/master input (I/O) and comparator 2 direct output (O). |
| 54 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with alternate function ePWM2A output with HRPWM channel (O). |
| 55 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with alternate functions ePWM1B output (O) and comparator 1 direct output (O). |
| 56 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with alternate function ePWM1A output with HRPWM channel (O). |
| 57 | VDDIO | power_in | Digital I/O buffer and flash power pin; a decoupling capacitor is to be placed on each VDDIO pin. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground. |
| 60 | VREGENZ | input | Internal regulator (VREG) enable with internal pull-down; connect directly to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply. |
| 61 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | General-purpose I/O 34 with alternate functions comparator 2 direct output (O) and comparator 3 direct output (O); GPIO34 is a glitch-prone pin during power-up when the internal VREG is used. |
| 62 | GPIO20/EQEP1A/COMP1OUT | bidirectional | General-purpose I/O 20 with alternate functions eQEP1 input A (I) and comparator 1 direct output (O). |
| 63 | GPIO21/EQEP1B/COMP2OUT | bidirectional | General-purpose I/O 21 with alternate functions eQEP1 input B (I) and comparator 2 direct output (O). |
| 64 | GPIO24/ECAP1/SPISIMOB | bidirectional | General-purpose I/O 24 with alternate functions enhanced capture 1 I/O (I/O) and SPI-B slave input/master output (I/O). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
TMS320F28031PAGQ - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
tms320f28031pagq-etched.step/tms320f28031pagq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28031pagq.step/tms320f28031pagq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (176 pp, sha256
cb9ccecfd6b5c484, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).