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HEF4052BTT-Q100

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by Ray

Nexperia Analog Switches, Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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HEF4052BTT-Q100

Nexperia · Analog Switches, Multiplexers · TSSOP-16

HEF4052BTT-Q100 from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2Y0 bidirectional Channel 0 independent input/output of switch bank 2. Connected to common 2Z when E=LOW and S2=LOW, S1=LOW. Analog signal path; RON typ 80 Ω at VDD-VEE = 10 V.
2 2Y2 bidirectional Channel 2 independent input/output of switch bank 2. Connected to common 2Z when E=LOW and S2=HIGH, S1=LOW. Bidirectional analog signal path.
3 2Z bidirectional Common output/input of switch bank 2. Routed to one of 2Y0..2Y3 as selected by S1/S2 when the E enable is LOW. Bidirectional analog signal.
4 2Y3 bidirectional Channel 3 independent input/output of switch bank 2. Connected to common 2Z when E=LOW and S2=HIGH, S1=HIGH. Bidirectional analog signal path.
5 2Y1 bidirectional Channel 1 independent input/output of switch bank 2. Connected to common 2Z when E=LOW and S2=LOW, S1=HIGH. Bidirectional analog signal path.
6 E input Active-LOW enable input (shown with overline on the datasheet). When LOW, the selected channel per S1/S2 is connected between nZ and the corresponding nYn. When HIGH, all switches are OFF (high impedance). Digital CMOS logic input.
7 VEE power_in Negative analog supply / substrate reference for the transmission gates. Referenced to VDD; range -18 V to +0.5 V (relative to VDD). Often tied to VSS for single-supply operation.
8 VSS power_in Digital ground / reference (0 V). All voltages in the datasheet referenced to VSS.
9 S2 input Digital select input, MSB of the 2-bit channel selector shared by both switch banks. Together with S1 selects one of nY0..nY3 to route to nZ when E is LOW.
10 S1 input Digital select input, LSB of the 2-bit channel selector shared by both switch banks. Together with S2 selects one of nY0..nY3 to route to nZ when E is LOW.
11 1Y3 bidirectional Channel 3 independent input/output of switch bank 1. Connected to common 1Z when E=LOW and S2=HIGH, S1=HIGH. Bidirectional analog signal path.
12 1Y0 bidirectional Channel 0 independent input/output of switch bank 1. Connected to common 1Z when E=LOW and S2=LOW, S1=LOW. Bidirectional analog signal path.
13 1Z bidirectional Common output/input of switch bank 1. Routed to one of 1Y0..1Y3 as selected by S1/S2 when the E enable is LOW. Bidirectional analog signal.
14 1Y1 bidirectional Channel 1 independent input/output of switch bank 1. Connected to common 1Z when E=LOW and S2=LOW, S1=HIGH. Bidirectional analog signal path.
15 1Y2 bidirectional Channel 2 independent input/output of switch bank 1. Connected to common 1Z when E=LOW and S2=HIGH, S1=LOW. Bidirectional analog signal path.
16 VDD power_in Positive supply voltage. Operating range 3 V to 15 V; absolute max -0.5 V to +18 V referenced to VSS. Also sets the digital input logic thresholds (VIH ≥ 3.5 V at VDD=5 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Interface
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • HEF4052BTT-Q100
  • HEF4052BT-Q100

CAD (KiCad official)

  • Symbol: HEF4052BTT-Q100
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 cc7ebf99a968f0c6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF