component
TPPM0301DR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPPM0301DR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
TPPM0301DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 5VAUX | input | 5-V auxiliary input; recommended V(5VAUX) is 4.5 V to 5.5 V, and it is the second-priority source after 5VCC. |
| 2 | 5VCC | input | 5-V main input, the highest-priority source; recommended V(5VCC) is 4.5 V to 5.5 V and it drives the low-dropout regulator to the 3.3-V output. |
| 3 | 3.3VOUT | output | Regulated 3.3-V output (3.135 V to 3.465 V at 400 mA) that requires a typical 4.7 µF load capacitance with minimal ESR for stability. |
| 4 | 3.3VAUX | input | 3.3-V auxiliary input, the lowest-priority source, recommended at 3 V to 3.6 V and passed to the output through the low-RDS(on) auxiliary switch. |
| 5 | GND | power_in | Ground terminal; terminals 5 to 8 form the integral fused lead frame used for heat spreading, and all voltages are referenced to GND. |
| 6 | GND | power_in | Ground terminal; terminals 5 to 8 form the integral fused lead frame used for heat spreading, and all voltages are referenced to GND. |
| 7 | GND | power_in | Ground terminal; terminals 5 to 8 form the integral fused lead frame used for heat spreading, and all voltages are referenced to GND. |
| 8 | GND | power_in | Ground terminal; terminals 5 to 8 form the integral fused lead frame used for heat spreading, and all voltages are referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 5-V main input voltage, recommended | V(5VCC) | 4.5 | 5.5 | V | 3 | ||
| 5-V auxiliary input voltage, recommended | V(5VAUX) | 4.5 | 5.5 | V | 3 | ||
| 3.3-V auxiliary input voltage, recommended | V(3.3VAUX) | 3 | 3.6 | V | 3 | ||
| Load capacitance, recommended | CL | 4.23 | 4.7 | 5.17 | µF | 3 | |
| Load current, recommended | IL | 0 | 400 | mA | 3 | ||
| Ambient temperature, recommended | TA | 0 | 70 | °C | 3 | ||
| Supply voltage, 5-V main input | V(5VCC) | 7 | V | Notes 1 and 2 | 3 | ||
| Auxiliary voltage, 5-V input | V(5VAUX) | 7 | V | Notes 1 and 2 | 3 | ||
| Auxiliary voltage, 3.3-V input | V(3.3VAUX) | 5 | V | Notes 1 and 2 | 3 | ||
| Absolute negative voltage on terminals | -0.5 | V | Note 2 | 3 | |||
| 3.3-V output current limit | I(LIMIT) | 1.5 | A | 3 | |||
| Continuous power dissipation | PD | 1 | W | see Note 3 | 3 | ||
| Electrostatic discharge susceptibility, human body model | V(HBMESD) | 2 | kV | human body model | 3 | ||
| Operating ambient temperature range | TA | 0 | 70 | °C | 3 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 3 | ||
| Operating junction temperature range | TJ | -5 | 120 | °C | 3 | ||
| Lead temperature (soldering, 10 second) | T(LEAD) | 260 | °C | soldering, 10 second | 3 | ||
| 5-V main input voltage | V(5VCC)/V(5VAUX) | 4.5 | 5 | 5.5 | V | 5-V inputs | 4 |
| Quiescent supply current from 5VCC or 5VAUX | I(Q) | 2.5 | 5 | mA | From 5VCC or 5VAUX terminals, IL = 0 to 400 mA | 4 | |
| Quiescent supply current from 3.3VAUX | I(Q) | 250 | 500 | µA | From 3.3VAUX terminal, IL = 0 A | 4 | |
| Output load current | IL | 0.4 | A | 4 | |||
| Output current limit | I(LIMIT) | 1 | 1.5 | A | 3.3VOUT = 0 V | 4 | |
| Thermal shutdown | T(TSD) | 150 | 180 | °C | 3.3VOUT output shorted to 0 V | 4 | |
| 3.3-V output voltage | V(3.3VOUT) | 3.135 | 3.3 | 3.465 | V | IL = 400 mA | 4 |
| Reverse leakage output current | Ilkg(REV) | 50 | µA | Tested for input that is grounded. 3.3VAUX, 5VAUX or 5VCC = GND, 3.3VOUT = 3.3 V | 4 | ||
| 5-V detect threshold voltage, low | V(TO_LO) | 3.85 | 4.05 | 4.25 | V | 5VAUX or 5VCC ↓ | 4 |
| 5-V detect threshold voltage, high | V(TO_HI) | 4.1 | 4.3 | 4.5 | V | 5VAUX or 5VCC ↑ | 4 |
| Auxiliary switch resistance | R(SWITCH) | 0.4 | Ω | 5VAUX = 5VCC = 0 V, 3.3VAUX = 3.3 V, IL = 150 mA | 4 | ||
| Line regulation voltage | ∆VO(∆VI) | 2 | mV | 5VAUX or 5VCC = 4.5 V to 5.5 V | 4 | ||
| Load regulation voltage | ∆VO(∆IO) | 40 | mV | 20 mA < IL < 400 mA | 4 | ||
| Dropout voltage | VI – VO | 1 | V | IL < 400 mA | 4 | ||
| Load capacitance | CL | 4.7 | µF | Minimal ESR to insure stability of regulated output | 4 | ||
| Thermal hysteresis | Thys | 15 | °C | 3.3VOUT output shorted to 0 V | 4 | ||
| Thermal impedance, junction-to-ambient | RθJA | 97 | °C/W | 4 | |||
| Thermal impedance, junction-to-case | RθJC | 38 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPPM0301DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tppm0301dr-etched.step/tppm0301dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tppm0301dr.step/tppm0301dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
3cd50e6426728b97, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).