Digitizes four differential inputs at once, each with its own 24-bit delta-sigma modulator and programmable gain amplifier, so phase between channels is preserved for energy and vibration measurement. A four-wire SPI moves conversion data at up to 32 kSPS per channel, and per-channel PGA gains up to 128 handle small sensor signals directly. Runs from a 2.7 to 3.6 V analog supply with a separate digital supply. Aimed at power metering and condition monitoring.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Analog supply, 2.7 V to 3.6 V. Connect a 1-µF decoupling capacitor to AGND.
2	AGND	power_in	Analog ground reference for AVDD and the ADC analog front-end.
3	AIN0P	input	Positive differential analog input, channel 0. Input range referenced to AGND with an AVDD+0.3 V ceiling.
4	AIN0N	input	Negative differential analog input, channel 0.
5	AIN1N	input	Negative differential analog input, channel 1.
6	AIN1P	input	Positive differential analog input, channel 1.
7	AIN2P	input	Positive differential analog input, channel 2.
8	AIN2N	input	Negative differential analog input, channel 2.
9	AIN3N	input	Negative differential analog input, channel 3.
10	AIN3P	input	Positive differential analog input, channel 3.
11	SYNC/RESET	input	Conversion synchronization or system reset, active low. Digital input referenced to DGND/DVDD.
12	CS	input	SPI chip select, active low. Enables the serial interface for the current transaction.
13	DRDY	output	Data-ready indicator, active low. Falls when a new conversion result is available in the output register.
14	SCLK	input	SPI serial data clock. Shifts DIN in and DOUT out on opposite edges.
15	DOUT	output	SPI serial data output. Presents conversion data and register-read responses.
16	DIN	input	SPI serial data input. Accepts commands and register writes.
17	CLKIN	input	Master clock input, nominal 8.192 MHz. Drives the modulator and internal digital filter timing.
18	CAP	power_out	Internal LDO regulator output. Connect a 220-nF capacitor to DGND; do not load externally.
19	DGND	power_in	Digital ground reference for DVDD and the digital I/O.
20	DVDD	power_in	Digital I/O supply, 2.7 V to 3.6 V. Connect a 1-µF decoupling capacitor to DGND.

Key specifications

Parameter	Value
Type	4-channel simultaneous-sampling delta-sigma ADC
Resolution	24-bit
Channels	4 differential
PGA gain	1 to 128 per channel
Data rate	Up to 32 kSPS/channel
Interface	SPI
Analog supply	2.7-3.6 V
Package	TSSOP-20

Ordering variants

ADS131M04IPWR (TSSOP-20, tape & reel)

CAD (KiCad official)

Symbol: Analog_ADC:ADS131M04xPW (KiCad official)
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (105 pp, sha256 487bfd27103d0bac, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF