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EPCQ16ASI8N
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Intel/Altera Programmable Logic Device (CPLDs/FPGAs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownEPCQ16ASI8N
Intel/Altera · Programmable Logic Device (CPLDs/FPGAs) · SOIC-8
EPCQ16ASI8N from Intel/Altera, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nCS | input | Active-low chip select that toggles at the beginning and end of a valid operation; when high the device is deselected and DATA[3:0] are tri-stated, and a falling edge is required after power up before any operation. |
| 2 | DATA1 | bidirectional | In AS x1 and x4 modes outputs serial data to the FPGA on falling DCLK edges during read or configuration, and acts as an input during quad input fast write bytes. |
| 3 | DATA2 | bidirectional | In AS x4 mode outputs serial data to the FPGA on falling DCLK edges during read or configuration operations; in AS x1 mode this pin must connect to VCC. |
| 4 | GND | power_in | Ground pin. |
| 5 | DATA0 | bidirectional | In AS x1 mode it is the data input for write or program, latched at rising DCLK edges; in AS x4 mode it is an I/O pin that inputs data during write and outputs data on falling DCLK edges during read or configuration. |
| 6 | DCLK | input | Serial clock provided by the FPGA; data on DATA[3:0] is latched into the device on rising DCLK edges and changes after the falling edge. |
| 7 | DATA3 | bidirectional | In AS x4 mode outputs serial data to the FPGA on falling DCLK edges during read or configuration operations; in AS x1 mode this pin must connect to VCC. |
| 8 | VCC | power_in | Connect the power pins to a 3.3-V power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Intel/Altera |
| Package | SOIC-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.6 | 4.6 | V | With respect to GND | 5 | |
| Input or output voltage (numeric lower bound only; upper bound is VCC+0.4) | VIO | -0.6 | V | With respect to GND | 5 | ||
| Storage temperature | TSTG | -65 | 150 | °C | No bias | 5 | |
| Transient voltage on any pin (numeric lower bound only; upper bound is VCC+2.0) | VIT | -2 | V | < 20ns transient relative to GND | 5 | ||
| Power dissipation | PD | 54 | mW | EPCQ16A | 5 | ||
| DC VCC or GND current | IMAX | 15 | mA | EPCQ16A | 5 | ||
| Supply voltage | VCC | 2.7 | 3.6 | V | 5 | ||
| Ambient temperature, operating | TA | -40 | 85 | °C | For industrial use | 5 | |
| Low-level input voltage (numeric lower bound only; max is 0.3 x VCC) | VIL | -0.5 | V | 6 | |||
| Low-level output voltage | VOL | 0.2 | V | EPCQ16A | 6 | ||
| Input leakage current | II | -2 | 2 | µA | VI = VCC or GND | 6 | |
| Tri-state output off-state current | IOZ | -2 | 2 | µA | VO = VCC or GND | 6 | |
| Input leakage | ILR | 12 | µA | 0≤/Reset<VCC | 6 | ||
| Input leakage | ILR | 1 | µA | /Reset = VCC | 6 | ||
| Pull-up resistance | RPR | 300 | 1000 | kΩ | 6 | ||
| VCC supply current, standby | ICC0 | 10 | 50 | µA | Standby | 6 | |
| VCC supply current, active | ICC1 | 1 | 15 | mA | During active power mode | 7 | |
| Load capacitance | CL | 30 | pF | AC measurement conditions | 6 | ||
| Input rise and fall times | TR, TF | 5 | ns | AC measurement conditions | 6 | ||
| Input pin capacitance | CIN | 6 | pF | VIN = 0 V; TA = 25 °C, VCC = 3.0 V | 7 | ||
| Output pin capacitance | COUT | 8 | pF | VOUT = 0 V; TA = 25 °C, VCC = 3.0 V | 7 |
CAD (KiCad official)
- Symbol:
EPCQ16ASI8N - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
epcq16asi8n-etched.step/epcq16asi8n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);epcq16asi8n.step/epcq16asi8n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Intel/Altera datasheet (38 pp, sha256
9e780703f73f2e7c, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).