component
LTC2484IDD#TRPBF
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLTC2484IDD#TRPBF
Analog Devices · Analog To Digital Converters (ADC) · DFN-10-EP(3x3)
LTC2484IDD#TRPBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDI | input | Serial data input, shifted in on the rising edge of SCK, used to select line-frequency rejection, input channel, temperature sensor and 2x speed mode. |
| 2 | VCC | power_in | Positive supply voltage, to be bypassed to GND (pin 8) with a 1µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible. |
| 3 | VREF | power_in | Positive reference input whose voltage can be any value between 0.1V and VCC, with the negative reference being GND (pin 8). |
| 4 | IN+ | input | Positive differential analog input that may range from GND - 0.3V to VCC + 0.3V, with the bipolar input range (IN+ - IN-) extending from -0.5·VREF to 0.5·VREF. |
| 5 | IN- | input | Negative differential analog input that may range from GND - 0.3V to VCC + 0.3V, forming the differential input pair with IN+ (pin 4). |
| 6 | CS | input | Active-LOW chip select that enables the digital I/O and wakes the ADC, where a LOW-to-HIGH transition during data output aborts the transfer and starts a new conversion. |
| 7 | SDO | tri_state | Three-state digital output that carries serial data during the data output period, is high impedance when CS is HIGH, and shows conversion status during conversion and sleep periods. |
| 8 | GND | power_in | Ground shared by analog, digital and reference grounds, which should be connected directly to a ground plane through a minimum impedance. |
| 9 | SCK | bidirectional | Serial clock that is an output in internal serial clock mode and an input in external serial clock mode, with a weak internal pull-up active in internal mode; the mode is set by the SCK level at power-up or at the most recent falling edge of CS. |
| 10 | fO | input | Digital frequency control input that selects the internal 307.2kHz oscillator when connected to GND, or may be driven by an external clock to change the output rate or digital filter rejection null. |
| 11 | GND | power_in | Exposed pad is ground and must be soldered to the PCB GND plane, though it may remain floating for prototyping purposes. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Data Acquisition |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resolution (No Missing Codes) | 24 | Bits | 0.1 ≤ VREF ≤ VCC, -FS ≤ VIN ≤ +FS (Note 5) | 2 | |||
| Integral Nonlinearity | 2 | ppm of VREF | 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) | 2 | |||
| Integral Nonlinearity | 10 | ppm of VREF | 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) | 2 | |||
| Offset Error | 0.5 | 2.5 | µV | 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN- ≤ VCC (Note 14) | 2 | ||
| Positive Full-Scale Error | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN- = 0.25VREF | 2 | |||
| Negative Full-Scale Error | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN- = 0.25VREF | 2 | |||
| Total Unadjusted Error | 15 | ppm of VREF | 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V; 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V; 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V | 2 | |||
| Internal PTAT Signal | 390 | 450 | mV | TA = 27°C | 2 | ||
| Input Common Mode Rejection DC | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Common Mode Rejection 50Hz ±2% | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Common Mode Rejection 60Hz ±2% | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Normal Mode Rejection 50Hz ±2% | 110 | 120 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 7) | 3 | ||
| Input Normal Mode Rejection 60Hz ±2% | 110 | 120 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 8) | 3 | ||
| Input Normal Mode Rejection 50Hz/60Hz ±2% | 87 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 9) | 3 | |||
| Reference Common Mode Rejection DC | 120 | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | ||
| Digital Input Low Level Voltage CS, fO, SDI | VIL | 0.5 | V | 2.7V ≤ VCC ≤ 5.5V | 4 | ||
| Digital Input Low Level Voltage SCK | VIL | 0.5 | V | 2.7V ≤ VCC ≤ 5.5V (Note 10) | 4 | ||
| Digital Input Current CS, fO, SDI | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VCC | 4 | |
| Digital Input Current SCK | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VCC (Note 10) | 4 | |
| Low Level Output Voltage SDO | VOL | 0.4 | V | IO = 1.6mA | 4 | ||
| Low Level Output Voltage SCK | VOL | 0.4 | V | IO = 1.6mA | 4 | ||
| Hi-Z Output Leakage SDO | IOZ | -10 | 10 | µA | 4 | ||
| IN+ DC Leakage Current | IDC_LEAK (IN+) | -10 | 1 | 10 | nA | Sleep Mode, IN+ = GND | 4 |
| IN- DC Leakage Current | IDC_LEAK (IN-) | -10 | 1 | 10 | nA | Sleep Mode, IN- = GND | 4 |
| VREF DC Leakage Current | IDC_LEAK (VREF) | -100 | 1 | 100 | nA | Sleep Mode, VREF = VCC | 4 |
| Supply Voltage | VCC | 2.7 | 5.5 | V | 4 | ||
| Supply Current Conversion Mode | ICC | 160 | 250 | µA | Conversion Mode (Note 12) | 4 | |
| Supply Current Sleep Mode | ICC | 1 | 2 | µA | Sleep Mode (Note 12) | 4 | |
| External Oscillator Frequency Range | fEOSC | 10 | 1000 | kHz | Note 15 | 5 | |
| External Oscillator High Period | tHEO | 0.125 | 100 | µs | 5 | ||
| External Oscillator Low Period | tLEO | 0.125 | 100 | µs | 5 | ||
| Conversion Time for 1x Speed Mode | tCONV_1 | 157.2 | 160.3 | 163.5 | ms | 50Hz Mode | 5 |
| Conversion Time for 1x Speed Mode | tCONV_1 | 131 | 133.6 | 136.3 | ms | 60Hz Mode | 5 |
| Conversion Time for 1x Speed Mode | tCONV_1 | 144.1 | 146.9 | 149.9 | ms | Simultaneous 50Hz/60Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 78.7 | 80.3 | 81.9 | ms | 50Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 65.6 | 66.9 | 68.2 | ms | 60Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 72.2 | 73.6 | 75.1 | ms | Simultaneous 50Hz/60Hz Mode | 5 |
| Internal SCK Duty Cycle | DISCK | 45 | 55 | % | Note 10 | 5 | |
| External SCK Frequency Range | fESCK | 4000 | kHz | Note 10 | 5 | ||
| External SCK Low Period | tLESCK | 125 | ns | Note 10 | 5 | ||
| External SCK High Period | tHESCK | 125 | ns | Note 10 | 5 | ||
| Internal SCK 32-Bit Data Output Time | tDOUT_ISCK | 0.81 | 0.83 | 0.85 | ms | Internal Oscillator (Notes 10, 12) | 5 |
| CS↓ to SDO Low | t1 | 0 | 200 | ns | 5 | ||
| CS↑ to SDO Hi-Z | t2 | 0 | 200 | ns | 5 | ||
| CS↓ to SCK↓ | t3 | 0 | 200 | ns | Note 10 | 5 | |
| CS↓ to SCK↑ | t4 | 50 | ns | Note 10 | 5 | ||
| SCK↓ to SDO Valid | tKQMAX | 200 | ns | 5 | |||
| SDO Hold After SCK↓ | tKQMIN | 15 | ns | Note 5 | 5 | ||
| SCK Set-Up Before CS↓ | t5 | 50 | ns | 5 | |||
| SCK Hold After CS↓ | t6 | 50 | ns | 5 | |||
| SDI Setup Before SCK↑ | t7 | 100 | ns | Note 5 | 5 | ||
| SDI Hold After SCK↑ | t8 | 100 | ns | Note 5 | 5 | ||
| Supply Voltage (absolute maximum) | VCC | -0.3 | 6 | V | Voltage to GND (Note 2) | 2 | |
| Storage Temperature Range | -65 | 125 | °C | 2 | |||
| Operating Temperature Range | TA | -40 | 85 | °C | LTC2484I | 2 | |
| Maximum Junction Temperature | TJMAX | 125 | °C | 2 | |||
| Junction-to-Ambient Thermal Resistance | θJA | 43 | °C/W | 2 | |||
| Output Noise | 0.6 | µVRMS | 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN- = IN+ ≤ VCC (Note 13) | 2 | |||
| Offset Error Drift | 10 | nV/°C | 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN- ≤ VCC | 2 | |||
| Positive Full-Scale Error Drift | 0.1 | ppm of VREF/°C | 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN- = 0.25VREF | 2 |
CAD (KiCad official)
- Symbol:
LTC2484IDD#TRPBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ltc2484idd-trpbf-etched.step/ltc2484idd-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc2484idd-trpbf.step/ltc2484idd-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (42 pp, sha256
6294e4f062f9f860, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).