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Contents

README

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MC79L15ACDR2G

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

MC79L15ACDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Vout power_out Regulated negative output of the MC79L15AC, specified at −15 V nominal with output limits of −14.25 V to −15.75 V at IO = 40 mA and VI = −23 V.
2 Vin power_in Negative unregulated input; the datasheet states the input must remain typically 2.0 V above the output voltage, even at the low point of the ripple.
3 Vin power_in Input pin listed as Vin for the SOIC-8 package; the datasheet gives no separate electrical limit for this pin beyond the input voltage requirements.
4 NC unconnected Listed as no connection (NC) in the SOIC-8 pinout; the datasheet assigns it no function.
5 GND power_in Common ground; the datasheet requires a common ground between the input and output voltages.
6 Vin power_in Input pin listed as Vin for the SOIC-8 package; the datasheet gives no separate electrical limit for this pin beyond the input voltage requirements.
7 Vin power_in Input pin listed as Vin for the SOIC-8 package; the datasheet gives no separate electrical limit for this pin beyond the input voltage requirements.
8 NC unconnected Listed as no connection (NC) in the SOIC-8 pinout; the datasheet assigns it no function.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage (TJ = +25 C) VO -14.4 -15 -15.6 Vdc TJ = +25 C 3
Input Regulation Regline 300 mV (TJ = +25 C) −17.5 Vdc VI −30 Vdc 3
Input Regulation Regline 250 mV (TJ = +25 C) −20 Vdc VI −30 Vdc 3
Load Regulation Regload 150 mV TJ = +25 C, 1.0 mA IO 100 mA 3
Load Regulation Regload 75 mV 1.0 mA IO 40 mA 3
Output Voltage VO -14.25 -15.75 Vdc −17.5 Vdc VI −Vdc, 1.0 mA IO 40 mA 3
Input Bias Current (TJ = +25 C) IIB 6.5 mA TJ = +25 C 3
Input Bias Current (TJ = +125 C) IIB 6 mA TJ = +125 C 3
Input Bias Current Change (line) IIB 1.5 mA −20 Vdc VI −30 Vdc 3
Input Bias Current Change (load) IIB 0.1 mA 1.0 mA IO 40 mA 3
Ripple Rejection RR 34 39 dB −18.5 VI −28.5 Vdc, f = 120 Hz 3
Output Noise Voltage VN 90 V TA = +25 C, 10 Hz f 100 kHz 3
Dropout Voltage /VI−VO/ 1.7 Vdc IO = 40 mA, TJ = +25 C 3
Input Voltage (−12, −15, −18 V device group) VI -35 Vdc −12, −15, −18 V 2
Storage Temperature Range Tstg -65 150 C 2
Junction Temperature TJ 150 C 2
Thermal Resistance, Junction-to-Ambient (SOIC-8) RJA 180 C/W Case 751 (SOIC-8), TA = 25 C, minimum recommended pad size 2
Thermal Resistance, Junction-to-Case (SOIC-8) RJC 45 C/W Case 751 (SOIC-8) 2
Operating Junction Temperature (MC79LXXAC grade) TJ 0 125 C MC79LXXAC 2

CAD (KiCad official)

  • Symbol: MC79L15ACDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mc79l15acdr2g-etched.step / mc79l15acdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc79l15acdr2g.step / mc79l15acdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (15 pp, sha256 3b8ec4831b4ba3d5, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF