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AGLN250V2-VQ100

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Microchip Tech Programmable Logic Device (CPLDs/FPGAs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersagln250v2-vq100factory-2.0.0extractor-text

Verified AGLN250V2-VQ100

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 100 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AGLN250V2-VQ100 · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 148-page datasheet
  • ✓distributor: lcsc C5235443, digikey AGLN250V2-VQ100-ND, mouser 494-AGLN250V2-VQ100
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-igm7zbtr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ agln250v2-vq100.kicad_sym✓ agln250v2-vq100.kicad_mod✓ agln250v2-vq100.step
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Contents

README

markdown

AGLN250V2-VQ100

Microchip Tech · Programmable Logic Device (CPLDs/FPGAs) · TQFP-100(14x14)

AGLN250V2-VQ100 from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
2 GAA2/IO67RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
3 IO66RSB3 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
4 GAB2/IO65RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
5 IO64RSB3 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
6 GAC2/IO63RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
7 IO62RSB3 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
8 IO61RSB3 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
9 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
10 GFB1/IO60RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
11 GFB0/IO59RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
12 VCOMPLF power_in Ground to the analog PLL power supply; tie to ground when the PLL is not used.
13 GFA0/IO57RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
14 VCCPLF power_in Analog PLL supply voltage, nominally 1.5 V or 1.2 V; Microsemi recommends tying it to VCC.
15 GFA1/IO58RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
16 GFA2/IO56RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
17 VCC power_in Core supply voltage to the FPGA core, 1.2 V or 1.5 V for IGLOO nano V2 devices; also powers the JTAG state machine.
18 VCCIB3 power_in I/O supply voltage for I/O bank 3, nominally 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
19 GFC2/IO55RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
20 GEC1/IO54RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
21 GEC0/IO53RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
22 GEA1/IO52RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
23 GEA0/IO51RSB3 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
24 VMV3 power_in Quiet supply voltage to the input buffers of I/O bank 3; must be connected to VCCIB3 of the same bank.
25 GNDQ power_in Quiet ground to the input buffers of the I/O banks; must always be connected to GND on the board.
26 GEA2/IO50RSB2 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
27 FF/GEB2/IO49RSB2 input Dedicated active-low FlashFreeze mode activation input when FlashFreeze is used; must not be left floating, otherwise it is a regular I/O.
28 GEC2/IO48RSB2 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
29 IO47RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
30 IO46RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
31 IO45RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
32 IO44RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
33 IO43RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
34 IO42RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
35 IO41RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
36 IO40RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
37 VCC power_in Core supply voltage to the FPGA core, 1.2 V or 1.5 V for IGLOO nano V2 devices.
38 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
39 VCCIB2 power_in I/O supply voltage for I/O bank 2, nominally 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
40 IO39RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
41 IO38RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
42 IO37RSB2 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
43 GDC2/IO36RSB2 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
44 GDB2/IO35RSB2 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
45 GDA2/IO34RSB2 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
46 GNDQ power_in Quiet ground to the input buffers of the I/O banks; must always be connected to GND on the board.
47 TCK input JTAG test clock input for boundary scan, ISP, and UJTAG; tie off through a resistor to GND if JTAG is unused.
48 TDI input JTAG serial test data input with an internal weak pull-up resistor.
49 TMS input JTAG test mode select controlling the IEEE 1532 boundary scan pins, with an internal weak pull-up resistor.
50 VMV2 power_in Quiet supply voltage to the input buffers of I/O bank 2; must be connected to VCCIB2 of the same bank.
51 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
52 VPUMP power_in Programming supply voltage, nominally 3.3 V for programming; can be left floating during normal operation.
53 NC unconnected No connect; not connected to circuitry within the device.
54 TDO output Serial JTAG test data output for boundary scan, ISP, and UJTAG.
55 TRST input Active-low JTAG boundary scan reset input with an internal weak pull-up resistor.
56 VJTAG power_in JTAG supply voltage, which can be run from 1.5 V to 3.3 V nominal, isolated in a separate I/O bank.
57 GDA1/IO33RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
58 GDC0/IO32RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
59 GDC1/IO31RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
60 IO30RSB1 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
61 GCB2/IO29RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
62 GCA1/IO27RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
63 GCA0/IO28RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
64 GCC0/IO26RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
65 GCC1/IO25RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
66 VCCIB1 power_in I/O supply voltage for I/O bank 1, nominally 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
67 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
68 VCC power_in Core supply voltage to the FPGA core, 1.2 V or 1.5 V for IGLOO nano V2 devices.
69 IO24RSB1 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
70 GBC2/IO23RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
71 GBB2/IO22RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
72 IO21RSB1 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
73 GBA2/IO20RSB1 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
74 VMV1 power_in Quiet supply voltage to the input buffers of I/O bank 1; must be connected to VCCIB1 of the same bank.
75 GNDQ power_in Quiet ground to the input buffers of the I/O banks; must always be connected to GND on the board.
76 GBA1/IO19RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
77 GBA0/IO18RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
78 GBB1/IO17RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
79 GBB0/IO16RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
80 GBC1/IO15RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
81 GBC0/IO14RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
82 IO13RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
83 IO12RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
84 IO11RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
85 IO10RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
86 IO09RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
87 VCCIB0 power_in I/O supply voltage for I/O bank 0, nominally 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
88 GND power_in Ground supply voltage to the core, I/O outputs, and I/O logic.
89 VCC power_in Core supply voltage to the FPGA core, 1.2 V or 1.5 V for IGLOO nano V2 devices.
90 IO08RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
91 IO07RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
92 IO06RSB0 bidirectional User I/O; input, output, tristate or bidirectional buffer compatible with the selected I/O standard.
93 GAC1/IO05RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
94 GAC0/IO04RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
95 GAB1/IO03RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
96 GAB0/IO02RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
97 GAA1/IO01RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
98 GAA0/IO00RSB0 bidirectional Global I/O with access to clock conditioning circuitry and the global network; can also be used as a regular I/O.
99 GNDQ power_in Quiet ground to the input buffers of the I/O banks; must always be connected to GND on the board.
100 VMV0 power_in Quiet supply voltage to the input buffers of I/O bank 0; must be connected to VCCIB0 of the same bank.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC core supply voltage VCC -0.3 1.65 V 18
JTAG DC voltage VJTAG -0.3 3.75 V 18
Programming voltage VPUMP -0.3 3.75 V 18
Analog power supply (PLL) VCCPLL -0.3 1.65 V 18
DC I/O buffer supply voltage VCCI -0.3 3.75 V 18
I/O input voltage VI -0.3 3.6 V 18
Storage temperature TSTG -65 150 °C 18
Junction temperature TJ 125 °C 18
Junction temperature, Extended Commercial TJ -20 85 °C Extended Commercial 19
1.5 V DC core supply voltage VCC 1.425 1.575 V 1.5 V DC core supply voltage 19
1.2 V-1.5 V wide range core voltage VCC 1.14 1.575 V IGLOO nano V2 devices only, operating at VCCI ≥ VCC 19
JTAG DC voltage VJTAG 1.4 3.6 V 19
Programming voltage, programming mode VPUMP 3.15 3.45 V Programming mode 19
Programming voltage, operation VPUMP 0 3.6 V Operation 19
PLL analog supply, 1.5 V DC core VCCPLL 1.425 1.575 V 1.5 V DC core supply voltage 19
PLL analog supply, wide range VCCPLL 1.14 1.575 V 1.2 V-1.5 V wide range core supply voltage 19
1.2 V DC I/O supply VCCI 1.14 1.26 V 1.2 V DC supply voltage 19
1.2 V DC wide range I/O supply VCCI 1.14 1.575 V 1.2 V DC wide range supply voltage 19
1.5 V DC I/O supply VCCI 1.425 1.575 V 1.5 V DC supply voltage 19
1.8 V DC I/O supply VCCI 1.7 1.9 V 1.8 V DC supply voltage 19
2.5 V DC I/O supply VCCI 2.3 2.7 V 2.5 V DC supply voltage 19
3.3 V DC I/O supply VCCI 3 3.6 V 3.3 V DC supply voltage 19
3.3 V DC wide range I/O supply VCCI 2.7 3.6 V 3.3 V DC wide range supply voltage 19
Input capacitance CIN 8 pF VIN = 0, f = 1.0 MHz 40
Input capacitance on clock pin CINCLK 8 pF VIN = 0, f = 1.0 MHz 40
Input leakage current IIL, commercial IIL 10 µA Commercial, 3.3 V LVTTL/LVCMOS 36
Input leakage current IIH, commercial IIH 10 µA Commercial, 3.3 V LVTTL/LVCMOS 36
Junction-to-case thermal resistance, VQFP 100 θjc 10 °C/W VQFP 100-pin 23
Junction-to-ambient thermal resistance, still air, VQFP 100 θja 35.3 °C/W VQFP 100-pin, still air 23
Junction-to-ambient thermal resistance, 200 ft/min, VQFP 100 θja 29.4 °C/W VQFP 100-pin, 200 ft./min. 23
Junction-to-ambient thermal resistance, 500 ft/min, VQFP 100 θja 27.1 °C/W VQFP 100-pin, 500 ft./min. 23
Flash*Freeze mode quiescent current, 1.2 V core IDD 20 µA AGLN250, typical 25°C, 1.2 V core 24
Flash*Freeze mode quiescent current, 1.5 V core IDD 34 µA AGLN250, typical 25°C, 1.5 V core 24
ICCA current, no Flash*Freeze, 1.2 V core ICCA 18 µA AGLN250, typical 25°C, 1.2 V core 25
ICCA current, no Flash*Freeze, 1.5 V core ICCA 44 µA AGLN250, typical 25°C, 1.5 V core 25

CAD (KiCad official)

  • Symbol: AGLN250V2-VQ100
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: agln250v2-vq100-etched.step / agln250v2-vq100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); agln250v2-vq100.step / agln250v2-vq100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (148 pp, sha256 7c3df8abbd28d8ee, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF