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Contents

README

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LWS60110AS

Lewa Micro · MOSFETs · SOP-8

LWS60110AS from Lewa Micro, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the P-channel MOSFET (internal body diode anode side); drain-to-source voltage rated -60 V.
2 S passive Source terminal of the P-channel MOSFET, tied in parallel with the other source pins.
3 S passive Source terminal of the P-channel MOSFET, tied in parallel with the other source pins.
4 G input Gate terminal; gate-to-source voltage limited to ±20 V with threshold of -1.6 V typical.
5 D passive Drain terminal; continuous drain current -4.0 A at TA=25℃ and pulsed -16 A.
6 D passive Drain terminal, tied in parallel with the other drain pins.
7 D passive Drain terminal, tied in parallel with the other drain pins.
8 D passive Drain terminal, tied in parallel with the other drain pins.

Key specifications

Parameter Value
Manufacturer Lewa Micro
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: LWS60110AS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: lws60110as-etched.step / lws60110as-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lws60110as.step / lws60110as.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lewa Micro datasheet (10 pp, sha256 6ea5953fb7f677c8, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF