component
MC74HC74ADG
Public Made by Adomby adom
onsemi Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC74ADG
onsemi · Flip Flops · SOIC-14
MC74HC74ADG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET 1 | input | Asynchronous Reset input of flip-flop 1, which forces Q1 low and Q1 inverted high when driven low. |
| 2 | DATA 1 | input | Data input of flip-flop 1, transferred to Q1 on the next positive-going clock edge. |
| 3 | CLOCK 1 | input | Clock input of flip-flop 1, which is triggered on the positive-going edge. |
| 4 | SET 1 | input | Asynchronous Set input of flip-flop 1, which forces Q1 high and Q1 inverted low when driven low. |
| 5 | Q1 | output | True output of flip-flop 1, able to drive 10 LSTTL loads. |
| 6 | ~{Q1} | output | Complementary output of flip-flop 1, able to drive 10 LSTTL loads. |
| 7 | GND | power_in | Ground pin (0 V reference) for the supply. |
| 8 | ~{Q2} | output | Complementary output of flip-flop 2, able to drive 10 LSTTL loads. |
| 9 | Q2 | output | True output of flip-flop 2, able to drive 10 LSTTL loads. |
| 10 | SET 2 | input | Asynchronous Set input of flip-flop 2, which forces Q2 high and Q2 inverted low when driven low. |
| 11 | CLOCK 2 | input | Clock input of flip-flop 2, which is triggered on the positive-going edge. |
| 12 | DATA 2 | input | Data input of flip-flop 2, transferred to Q2 on the next positive-going clock edge. |
| 13 | RESET 2 | input | Asynchronous Reset input of flip-flop 2, which forces Q2 low and Q2 inverted high when driven low. |
| 14 | VCC | power_in | Positive supply voltage, recommended 2.0 to 6.0 V (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage | Vin | -0.5 | V | Referenced to GND; max is VCC + 0.5 V | 2 | ||
| DC Output Voltage | Vout | -0.5 | V | Referenced to GND; max is VCC + 0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | per pin | 2 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 2 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | SOIC package; derate -7 mW/C from 65 to 125C | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | C | 2 | ||
| Lead Temperature | TL | 260 | C | 1 mm from case for 10 seconds, SOIC package | 2 | ||
| DC Supply Voltage | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage | Vin, Vout | 0 | V | Referenced to GND; max is VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | C | 2 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figures 1, 2, 3) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 600 | ns | VCC = 3.0 V (Figures 1, 2, 3) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figures 1, 2, 3) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figures 1, 2, 3) | 2 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at -55 to 25C, 85C, 125C | 3 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Minimum High-Level Output Voltage | VOH | 2.48 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ <= 2.4 mA; -55 to 25C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; -55 to 25C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.48 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ <= 5.2 mA; -55 to 25C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ <= 20 uA; same at all temps | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ <= 2.4 mA; -55 to 25C | 3 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | Vin = VCC or GND; VCC = 6.0 V; -55 to 25C | 3 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | Vin = VCC or GND; VCC = 6.0 V; 85C and 125C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 2 | µA | Vin = VCC or GND; Iout = 0 uA; VCC = 6.0 V; -55 to 25C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 20 | µA | Vin = VCC or GND; Iout = 0 uA; VCC = 6.0 V; 85C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 80 | µA | Vin = VCC or GND; Iout = 0 uA; VCC = 6.0 V; 125C | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 6 | MHz | VCC = 2.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 15 | MHz | VCC = 3.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 30 | MHz | VCC = 4.5 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 35 | MHz | VCC = 6.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 100 | ns | VCC = 2.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 75 | ns | VCC = 3.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 20 | ns | VCC = 4.5 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Propagation Delay, Clock to Q or Q̄ | tPLH, tPHL | 17 | ns | VCC = 6.0 V; CL = 50 pF; -55 to 25C | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | -55 to 25C, 85C and 125C | 3 | ||
| Minimum Setup Time, Data to Clock | tsu | 80 | ns | VCC = 2.0 V; -55 to 25C | 4 | ||
| Minimum Setup Time, Data to Clock | tsu | 35 | ns | VCC = 3.0 V; -55 to 25C | 4 | ||
| Minimum Setup Time, Data to Clock | tsu | 16 | ns | VCC = 4.5 V; -55 to 25C | 4 | ||
| Minimum Setup Time, Data to Clock | tsu | 14 | ns | VCC = 6.0 V; -55 to 25C | 4 | ||
| Minimum Pulse Width, Clock | tw | 60 | ns | VCC = 2.0 V; -55 to 25C | 4 | ||
| Minimum Pulse Width, Clock | tw | 25 | ns | VCC = 3.0 V; -55 to 25C | 4 | ||
| Minimum Pulse Width, Clock | tw | 12 | ns | VCC = 4.5 V; -55 to 25C | 4 | ||
| Minimum Pulse Width, Clock | tw | 10 | ns | VCC = 6.0 V; -55 to 25C | 4 | ||
| Power Dissipation Capacitance (Per Flip-Flop) | CPD | 32 | pF | Typical @ 25°C, VCC = 5.0 V | 3 |
CAD (KiCad official)
- Symbol:
MC74HC74ADG - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hc74adg-etched.step/mc74hc74adg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc74adg.step/mc74hc74adg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
7e4e1b23932092f6, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).