CA-IS3720CLS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDA	power_in	A-side supply voltage, specified over 3.0 V to 5.5 V (3.3 V typical) as a recommended operating condition.
2	VI1	input	Channel 1 A-side logic input on the CA-IS3720C; input thresholds are 0.7 x VDDI (high) and 0.3 x VDDI (low), per the electrical characteristics.
3	VI2	input	Channel 2 A-side logic input on the CA-IS3720C; input thresholds are 0.7 x VDDI (high) and 0.3 x VDDI (low), per the electrical characteristics.
4	GNDA	power_in	A-side ground reference point for the isolator's input side.
5	GNDB	power_in	B-side ground reference point for the isolator's output side.
6	VO2	output	Channel 2 B-side logic output on the CA-IS3720C; for the L-suffix part this output goes Low when the input-side supply is lost, with drive limited to 4 mA low-level (IOL) at 5 V.
7	VO1	output	Channel 1 B-side logic output on the CA-IS3720C; for the L-suffix part this output goes Low when the input-side supply is lost, with drive limited to 4 mA low-level (IOL) at 5 V.
8	VDDB	power_in	B-side supply voltage, specified over 3.0 V to 5.5 V (3.3 V typical) as a recommended operating condition.

Key specifications

Parameter	Value
Manufacturer	Chipanalog
Package	SOIC-8
Category	Signal Isolation Devices
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDDA, VDDB	VDDA, VDDB	3	3.3	5.5	V		6
VDD undervoltage threshold, rising	VDD（UVLO+）	2.55	2.7	2.85	V		6
VDD undervoltage threshold, falling	VDD（UVLO‐）	2.35	2.5	2.65	V		6
VDD UVLO hysteresis	VHYS（UVLO）	150	200	270	mV		6
High-level output current	IOH	-4			mA	VDDO1 = 5V	6
High-level output current	IOH	-2			mA	VDDO1 = 3.3V	6
Low-level output current	IOL			4	mA	VDDO1 = 5V	6
Low-level output current	IOL			2	mA	VDDO1 = 3.3V	6
Signal data rate	DR	0		40	Mbps		6
Ambient temperature	TA	-40	27	125	°C		6
Supply voltage VDDA, VDDB	VDDA, VDDB	-0.5		7	V		6
Input voltage VIx	VIN	-0.5			V		6
Output current	IO	-20		20	mA		6
Junction temperature	TJ			150	°C		6
Storage temperature range	TSTG	-65		150	°C		6
ESD human body model	VESD	-8000		8000	V	HBM, ANSI/ESDA/JEDEC JS-001, same-side pins	6
ESD charged device model	VESD	-2000		2000	V	CDM, JEDEC JESD22-C101, all pins	6
Maximum power dissipation	PD			60	mW	VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, 20MHz 50% duty square input	7
Maximum power dissipation, side A	PDA			20	mW		7
Maximum power dissipation, side B	PDB			40	mW		7
Output voltage logic low, 5V	VOL		0.2	0.4	V	IOL = 4mA; 图 8‐1	10
Input high leakage current	IIH			20	µA	VIH = VDDI1 at VIx	10
Input low leakage current	IIL	-20			µA	VIL = 0V at VIx	10
Common-mode transient immunity, 5V	CMTI	100	150		kV/µs	VI = VDDI1 or 0V, VCM = 1200V; 图 8‐3	10
Output voltage logic low, 3.3V	VOL		0.2	0.4	V	IOL = 2mA; 图 8‐1	10
Input high leakage current, 3.3V	IIH			20	µA	VIH = VDDI1 at VIx	10
Input low leakage current, 3.3V	IIL	-20			µA	VIL = 0V at VIx	10
Common-mode transient immunity, 3.3V	CMTI	100	150		kV/µs	VI = VDDI1 or 0V, VCM = 1200V; 图 8‐3	10
Supply current DC, side A, 5V	IDDA		1	2.1	mA	DC, VIN = 0V (CA‐IS3720CL)	11
Supply current DC, side B, 5V	IDDB		2.9	5	mA	DC, VIN = 0V (CA‐IS3720CL)	11
Supply current 1Mbps, side A, 5V	IDDA		2.5	4.4	mA	1Mbps (500kHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current 1Mbps, side B, 5V	IDDB		3.1	5.3	mA	1Mbps (500kHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current 10Mbps, side A, 5V	IDDA		3	5.1	mA	10Mbps (5MHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current 10Mbps, side B, 5V	IDDB		3.9	6.5	mA	10Mbps (5MHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current 40Mbps, side A, 5V	IDDA		3.4	5.7	mA	40Mbps (20MHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current 40Mbps, side B, 5V	IDDB		6.5	10.4	mA	40Mbps (20MHz), all inputs 50% duty, 5V square, CL = 15pF	11
Supply current DC, side A, 3.3V	IDDA		1	2.1	mA	DC, VIN = 0V (CA‐IS3720CL)	12
Supply current DC, side B, 3.3V	IDDB		2.8	4.8	mA	DC, VIN = 0V (CA‐IS3720CL)	12
Supply current 1Mbps, side A, 3.3V	IDDA		2.4	4.2	mA	1Mbps (500kHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Supply current 1Mbps, side B, 3.3V	IDDB		3	5.1	mA	1Mbps (500kHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Supply current 10Mbps, side A, 3.3V	IDDA		2.8	4.8	mA	10Mbps (5MHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Supply current 10Mbps, side B, 3.3V	IDDB		3.4	5.7	mA	10Mbps (5MHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Supply current 40Mbps, side A, 3.3V	IDDA		3.2	5.4	mA	40Mbps (20MHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Supply current 40Mbps, side B, 3.3V	IDDB		5	8.7	mA	40Mbps (20MHz), all inputs 50% duty, 3.3V square, CL = 15pF	12
Data rate	DR	0		40	Mbps		13
Minimum pulse width	PWmin	20			ns		13
Propagation delay	tPLH, tPHL		22	35	ns	图 8‐1	13
Pulse width distortion	PWD		2.5	7	ns		13
Channel-to-channel output skew, same direction	tsk(o)		1	3	ns	same-direction channels	13
Part-to-part channel output skew	tsk(pp)		1	7	ns		13
Output rise time	tr		2.5	4.8	ns	图 8‐1	13
Output fall time	tf		2.5	4.8	ns	图 8‐1	13
Default output delay from input power down	tDO		10	15	ns	图 8‐2	13
Startup time	tSU		25	37	µs		13
Thermal resistance junction to ambient, SOIC8-NB(S)	RθJA		109		°C/W	SOIC8-NB(S)	7
Input capacitance, 5V	CI		2		pF	VI = VDD/2 + 0.4×sin(2πft), f = 1MHz, VDD = 5V	10
Input capacitance, 3.3V	CI		2		pF	VI = VDD/2 + 0.4×sin(2πft), f = 1MHz, VDD = 3.3V	10
Output impedance, 5V	ZO		50		Ω		10
Output impedance, 3.3V	ZO		50		Ω		10

CAD (KiCad official)

Symbol: CA-IS3720CLS
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ca-is3720cls-etched.step / ca-is3720cls-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3720cls.step / ca-is3720cls.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Chipanalog datasheet (24 pp, sha256 24fee350c7266eeb, retrieved 2026-11-04, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CA-IS3720CLS

Verified CA-IS3720CLS

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README