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Contents

README

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TPS2015DR

Texas Instruments · Power Distribution Switches · SOIC-8

TPS2015DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the device; all device voltages (input, output, EN) are specified with respect to GND.
2 IN power_in Input voltage to the power switch, recommended operating range 4 V to 5.5 V and absolute maximum -0.3 V to 7 V; the datasheet says IN pins must be connected in parallel with pin 3 to minimize voltage drop.
3 IN power_in Input voltage to the power switch, recommended operating range 4 V to 5.5 V and absolute maximum -0.3 V to 7 V; connect in parallel with pin 2 to minimize voltage drop.
4 EN input Enable input: logic low turns the power switch on and logic high turns it off, compatible with TTL and CMOS levels (VIH 2 V min, VIL 0.8 V max for 4 V ≤ VI ≤ 5.5 V), with a recommended range of 0 V to 5.5 V and absolute maximum of 7 V.
5 OC output Open-drain overcurrent logic output that is asserted active low during an overload or short-circuit fault and remains asserted until the fault is removed; low-level output voltage is specified as 0.3 V at 0°C ≤ TJ ≤ 125°C.
6 OUT power_out Power switch output (high-side N-channel MOSFET, 95 mΩ max at 5 V input); recommended continuous output current is 0 to 1 A for TPS2015, and output is limited to a constant current during overload.
7 OUT power_out Power switch output; connect in parallel with pins 6 and 8 to minimize voltage drop and power dissipation, as recommended by the application notes.
8 OUT power_out Power switch output; connect in parallel with pins 6 and 7 to minimize voltage drop and power dissipation, as recommended by the application notes.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: TPS2015DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps2015dr-etched.step / tps2015dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2015dr.step / tps2015dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 ef3947d44e45a981, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF